AVS 66th International Symposium & Exhibition
    Electronic Materials and Photonics Division Thursday Sessions
       Session EM+AP+MS+NS+TF-ThM

Paper EM+AP+MS+NS+TF-ThM2
Crystalline InP Growth and Device Fabrication Directly on Amorphous Dielectrics at Temperatures below 400oC for Future 3D Integrated Circuits

Thursday, October 24, 2019, 8:20 am, Room A214

Session: Advanced Processes for Interconnects and Devices
Presenter: Debarghya Sarkar, University of Southern California
Authors: D. Sarkar, University of Southern California
Y. Xu, University of Southern California
S. Weng, University of Southern California
R. Kapadia, University of Southern California
Correspondent: Click to Email
A fundamental requirement to realize 3D integrated circuits is the ability to integrate single crystal semiconductor devices on the back-end of functional layers within a thermal budget of ~400 oC. Present state-of-the-art methods involve wafer bonding or epitaxial growth and transfer, since directly growing on amorphous materials by traditional epitaxial growth processes like MOCVD and MBE would give polycrystalline films with submicron-scale grains. To that end, a newly introduced and actively developing growth method called Templated Liquid Phase (TLP) has demonstrated the ability to achieve single crystal compound semiconductor mesas of areal dimension ~ 10um diameter on diverse amorphous substrates. While previous demonstrations of TLP growth were at temperatures around 500-600 oC, in this presentation we would discuss some of the recent material characteristics and device results achieved and insights obtained, for crystalline InP mesas grown on amorphous dielectrics at temperatures below 400 oC. InP nucleation and growth was obtained for temperatures 360 oC down to 200 oC. Morphological variations of the grown crystals observed under different growth conditions (temperature, pressure, precursor flux) and strategies to obtain compact macro-defect free crystal growth would be presented. Contrary to general expectation of poor optoelectronic quality at these lower temperatures, the room temperature steady-state photoluminescence shows peak position and full width at half maximum comparable to that of commercial InP wafer. External quantum efficiency is within an order of magnitude of single crystal commercial wafer at optimal growth conditions. Back-gated phototransistor was fabricated using low temperature InP grown directly on the amorphous gate oxide, and with all processing steps below the thermal budget of 400 oC. A typical device showed reasonable ON-OFF ratio of about 3 orders of magnitude, with peak responsivity of 20 A/W at Vgs=3.2V and Vds=2.1V under an irradiance of 4 mW/cm2 of broadband light. In summary, this technology could potentially open up a viable avenue to realize 3D integrated circuits by enabling integration of high performance electronic and optoelectronic devices on the back-end of functional layers within the acceptable thermal budget of 4000C.