Invited Paper EM+2D+AP+NS+PS-TuM1
Performance Modeling and Design for Spintronic Logic and Memory Devices

Tuesday, October 22, 2019, 8:00 am, Room A214

As scaling conventional logic and memory devices becomes more and more challenging, there is a global search for novel materials and devices that can augment mainstream technologies used for data storage and processing. To this end, spintronic materials and devices are promising candidates as they provide dense non-volatile storing elements that enable novel computing paradigms such as in memory-computing and neural networks.

This talk will present physical models for various read and write spintronic mechanisms and quantifies the potential performances of Boolean circuits based on various spintronic logic devices. It will be shown that without major breakthroughs such circuits will not be able to compete with their CMOS counterparts. However, novel circuit paradigms that take advantage of the physics of these devices can potentially provide significant benefits. For example, cellular neural networks based on spintronic devices are projected to perform better compared to their analog CMOS implementation.

While spin-transfer-torque random access memory (STT-RAM) is becoming commercially available, it suffers from relatively large switching currents that limits its density and causes reliability challenges. Novel read and write mechanisms such as spin-orbit torque or magneto-electric effects can potentially address or partially mitigate some of these challenges. In this talk, the array-level potential performance of various magnetic memory devices will be quantified and benchmarked.