| AVS 65th International Symposium & Exhibition | |
| Thin Films Division | Wednesday Sessions |
| Session TF+EM+MI-WeM |
| Session: | Thin Film Processes for Electronics and Optics I |
| Presenter: | Aniruddha Joi, Lam Research Corporation |
| Authors: | D. Dictus, Lam Research Corporation, Belgium A. Joi, Lam Research Corporation G. Alessio Verni, Lam Research Corporation, Belgium K. Vandersmissen, Imec, Belgium B. Frees, Lam Research Corporation, Belgium Y. Yezdi, Lam Research Corporation |
| Correspondent: | Click to Email |
Just like atomic layer deposition in the gas phase, electrochemical atomic layer deposition in the liquid phase holds the promise of delivering very good conformality and uniformity for nm-thick film deposition by using surface limited reactions. Up to today however, there is no industry in which such process has been scaled up from cm-size coupons to industrial-scale substrates. In this paper, the scale up of electrochemical ALD of Cu is reported and it is demonstrated that this process can be used to fill <20 nm Cu interconnect lines as required for future microchip technology nodes.
The e-ALD process is a cyclic process that consists of a step in which a monolayer of Zn is deposited at a potential below the one, at which, Zn would grow multilayers (underpotential deposition), followed by a step in which the zinc is spontaneously displaced by Cu when the substrate is allowed to drift to the open circuit potential (surface limited replacement reaction, SLRR). By cycling between potentiostatic Zn deposition and open-circuit steps, Cu films can be grown in layer-by-layer fashion.
In contrast to classical electroplating processes, e-ALD processes do not require significant overpotential to create uniform nucleation. Also, current densities are small since the deposited amount of material per cycle is low. Therefore, the e-ALD process can be used to deposit Cu with atomic layer thickness control on substrates with high resistivity which gives the advantage of being able to plate on very thin (sub-20 A) liner materials.
Development of the e-ALD process is done on a Sabre electroplating tool from Lam Research on 300 mm substrates. These substrates contain a thin layer of Ru or Co on which the copper is deposited. The e-ALD process forms the seed layer for further metallization of the interconnect or can by itself fill the narrow interconnect lines.
We will demonstrate that good thickness uniformity can be achieved on 300 mm substrates with initial sheet resistance up to 1000 Ohm/sq and that filling of interconnect lines with dimensions smaller than 14 nm is achieved. Test chips containing our new Cu deposition process show high yield and the Cu interconnect lines have low resistance. This demonstrates the potential use of this new production method in future technology nodes.