AVS 65th International Symposium & Exhibition
    Plasma Science and Technology Division Wednesday Sessions
       Session PS+AS+EL+EM+SE-WeM

Paper PS+AS+EL+EM+SE-WeM4
Invited Talk-Future Stars of AVS Session: Low-Temperature Growth for 3D Integration of van der Waals Materials

Wednesday, October 24, 2018, 9:00 am, Room 104B

Session: Current and Future Stars of the AVS Symposium I
Presenter: Christopher L. Hinkle, University of Texas at Dallas
Correspondent: Click to Email

The integration of novel logic and memory devices, fabricated from van der Waals materials, into CMOS process flows with a goal of improving system-level Energy-Delay-Product (EDP) for data abundant applications will be discussed. Focusing on materials growth and integration techniques that utilize non-equilibrium, kinetically restricted strategies, coupled with in-situ characterization, enables the realization of atomic configurations and materials that are challenging to make but once attained, display enhanced and unique properties. These strategies become necessary for most future technologies where thermal budgets are constrained and conformal growth over selective areas and 3-dimensional structures are required.

In this work, we demonstrate the high-quality MBE heterostructure growth of various layered materials by van der Waals epitaxy (VDWE). The coupling of different types of van der Waals materials including transition metal dichalcogenide thin films (e.g., WSe2, WTe2, HfSe2), helical Te thin films, and topological insulators (e.g., Bi­2Se3) allows for the fabrication of novel electronic devices that take advantage of unique quantum confinement and spin-based characteristics. We demonstrate how the van der Waals interactions allow for heteroepitaxy of significantly lattice-mismatched materials without strain or misfit dislocations. We will discuss TMDs, Te, and TIs grown on atomic layer deposited (ALD) high-k oxides on a Si platform as well as flexible substrates and demonstrate field-effect transistors with back-end-of-line (<450 °C) and even flexible plastics (<200 °C) compatible fabrication temperatures. High performance transistors with field-effect mobilities as high as 700 cm2/V-s are demonstrated. The achievement of high-mobility transistor channels at low processing temperatures shows the potential for integrating van der Waals materials into new technologies.

This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor Research Corporation program sponsored by MARCO and DARPA. This work is also supported in part by NEWLIMITS, a center in nCORE, a Semiconductor Research Corporation (SRC) program sponsored by NIST through award number 70NANB17H041.