AVS 65th International Symposium & Exhibition
    MEMS and NEMS Group Wednesday Sessions
       Session MN+NS+PS-WeM

Paper MN+NS+PS-WeM4
Full Wafer Thickness Through Silicon Vias for MEMS Devices

Wednesday, October 24, 2018, 9:00 am, Room 202B

Session: IoT Session: Multiscale Manufacturing: Enabling Materials and Processes
Presenter: Andrew Hollowell, Sandia National Laboratories
Authors: A.E. Hollowell, Sandia National Laboratories
E. Baca, Sandia National Laboratories
D. Dagel, Sandia National Laboratories
M.B. Jordan, Sandia National Laboratories
L. Menk, Sandia National Laboratories
K. Musick, Sandia National Laboratories
T. Pluym, Sandia National Laboratories
J. McClain, Sandia National Laboratories
Correspondent: Click to Email

A significant amount of development has been achieved integrating TSVs with standard silicon (Si) substrates; however, there are unique challenges associated with integrating TSVs with MEMS substrates. Industry has achieved TSV integration through a dependence on substrate thinning, a TSV reveal approach. However, often these MEMS devices depend on the thickness of the substrate for controlling the radius of curvature of the substrate, such as throughout Sandia’s ultra-planar multilevel MEMS technology (SUMMiTTM). TSV filling relies on tight control of the fluid kinetics during the electroplating process and the ability to balance the diffusion of Cu2+ and organic suppressor molecules throughout the depth of the via in order to realize a void-free fill of the TSV. In this work we have extended the filling model for 60 μm deep TSVs, developed by Tom Moffat and Dan Josell, up to 675 μm deep TSVs.

In addition to the thickness constraints for MEMS integration, often MEMS devices are realized through unique release processes and are dependent on high temperature anneals. The most common release process is a hydrofluoric acid (HF) based release to selectively remove supporting oxide films and preserve the Si features that make up the MEMS components. The necessity to release structure in selective etchants presents additional challenges for integrating TSVs with MEMS components. We have overcome this challenge through the integration of additional capping layers which are selectively removed after the MEMS release. In order to accommodate the need for high temperature anneals we have removed the use of metal in the MEMS device and instead used doped silicon. The Cu TSVs are then integrated with the device after all the high temperature anneals are complete, making direct electrical contact to the doped Si. In this work, we present our integration approach for mating Cu TSVs with doped Si MEMS contacts and our plating approach for superfilling 675 μm deep, 100 μm wide TSVs.

This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. SAND2018-5012 A.