Invited Paper EM+MP+PS-MoM8
The Role of Selective Processes in the Atomic Scale Era

Monday, October 22, 2018, 10:40 am, Room 101A

The semiconductor industry has reached the point where devices are approaching atomic scales. But continued scaling presents a number of new challenges to our industry. First, there is no longer plenty of room at the bottom, which has forced device makers to scale upward by adopting three dimensional device structures and architectures. This has resulted in a drastic increase in the aspect ratios encountered during chip manufacturing. In addition, even with the advent of EUV lithography it will be necessary to employ multi-patterning technologies in order to fabricate the sub-lithographic features necessary to scale further. Multi-patterning requires multiple masks per layer which presents a challenge in terms of aligning masks to each other within a layer, and from layer to layer as the chip is fabricated. Self-aligned process flows such as self-aligned blocks, fully self-aligned vias, and self-aligned contacts are being employed to increase the margin of allowable edge placement error (EPE) for aligning feature and layers to each other at the cost of additional process complexity as well as exacerbating the problem of ever-increasing aspect ratios. Finally, functional films at useful thicknesses need to be accommodated within the volume of the device without voids or seams that can impact chip yields through degraded electrical performance or by providing a source of particles or foreign material.

To overcome these difficulties it is necessary to begin transitioning from the current top down manufacturing paradigm to a bottom up or additive manufacturing style. Selective depositions and etches represent a path to make this transition for devices makers. Self-aligned process flows already make use of etch selectivity between materials in order to achieve feature self-alignment, but isotropic and anisotropic selective depositions can provide additional advantages. Because area selective depositions are inherently self-aligned to the target material, they can enable new process flows for self-alignment. In addition, anisotropic feature filling can be used to fill high aspect ratio, or reentrant features on the chip without deleterious voids and seems as well as reducing the overburden needed for chemical mechanical polishing (CMP). And selective depositions can also be used to avoid or relieve the crowding of functional films within devices or other structures. In this presentation we seek to illustrate, with examples of new processes currently under investigation, how selective depositions and etches can enable future manufacturing nodes by introducing additive processing into the manufacturing flow.