AVS 65th International Symposium & Exhibition
    Extending Additive Manufacturing to the Atomic Scale Focus Topic Wednesday Sessions
       Session AM+MP+NS-WeA

Paper AM+MP+NS-WeA7
Electrical Transport Properties of Si:P δ-layer Devices

Wednesday, October 24, 2018, 4:20 pm, Room 102B

Session: Atomic Scale Manipulation with SPM
Presenter: Ranjit Kashid, National Institute of Standards and Technology (NIST)
Authors: R. Kashid, National Institute of Standards and Technology (NIST)
X. Wang, National Institute of Standards and Technology (NIST)
Namboodiri, National Institute of Standards and Technology (NIST)
J. Hagmann, National Institute of Standards and Technology (NIST)
S.W. Schmucker, University of Maryland College Park
J. Wyrick, National Institute of Standards and Technology (NIST)
C. Richter, National Institute of Standards and Technology (NIST)
R.M. Silver, National Institute of Standards and Technology (NIST)
Correspondent: Click to Email

Si:P has been realized as one of the ideal systems for donor-based quantum computation. Site-selective doping of phosphorous atoms at the atomic scale using Scanning Tunneling Microscopy (STM) lithography on the Si(100) 2×1:H surface enables the fabrication of these devices. In the past, our group has demonstrated that degenerately doped & well confined Si:P monolayers can be fabricated using phosphine dosing and low-temperature Molecular Beam Epitaxy (MBE). In addition, a wide range of 1D and 2D nanoscale devices can be fabricated by combining STM lithography and low-temperature MBE. Here, we present magnetotransport and low-frequency 1/f noise measurements on degenerately doped 1D nanowires, 2D Hall Bars, and van der Pauw structures defined using STM lithography. Specifically, we investigate the dephasing mechanism and present a comparative analysis of transport between STM patterned and mesa etched Si:P δ-layer van der Pauw structures to further elucidate the effects of STM patterning on transport properties.