| AVS 65th International Symposium & Exhibition | |
| Extending Additive Manufacturing to the Atomic Scale Focus Topic | Wednesday Sessions |
| Session AM+MP+NS-WeA |
| Session: | Atomic Scale Manipulation with SPM |
| Presenter: | Andreas Fuhrer, IBM Research - Zurich, Switzerland |
| Authors: | T. Skeren, IBM Research - Zurich, Switzerland N. Pascher, IBM Research - Zurich, Switzerland S.A. Köster, IBM Research - Zurich, Switzerland A. Fuhrer, IBM Research - Zurich, Switzerland |
| Correspondent: | Click to Email |
Since the invention of the first bipolar transistor, integrated circuits have evolved to incredibly complex, ultra-scaled devices with on the order of 109 transistors per chip. Even if these devices no longer rely on bipolar technology, excellent control of highly doped regions is still a critical factor for device performance. Moreover, single dopant atoms in a silicon crystal or nanoscale silicon transistors are thought to be candidates for spin qubits with a long spin lifetime.
The hydrogen resist lithography technique is capable of preparing atomic scale planar dopant devices. This is enabled by a large difference in chemical reactivity of the bare and hydrogen passivated Si (001): 2x1 surface. Using a scanning tunneling microscope (STM), the hydrogen layer of the H:Si (001) surface is locally desorbed with nanometer precision, exposing areas of reactive Si. When a gaseous dopant precursor such as phosphine or diborane is introduced, the hydrogen layer acts as a resist and the dopants stick only to the desorbed areas. Compared to conventional fabrication methods, hydrogen resist lithography enables degenerate d-doping with sub-nanometer lateral resolution and abrupt doping profiles.
We have extended the hydrogen-resist technique to p-type doping with diborane and present electrical transport measurements on p-type dopant wires and a simple planar pn-junction fabricated by STM patterning.
In addition, we have developed a CMOS compatible device platform for STM-based atomic-scale device fabrication. The scheme uses pre-fabricated samples with electrical contacts and alignment markers and a hydrogen terminated, reconstructed Si:H(001) surface that is protected from the ambient environment by a capping chip.
The sample surface can be used directly for STM-patterning and atomic device fabrication after in-situ removal of this capping chip. After STM device-fabrication the samples are reintegrated into the CMOS workflow by hydrophobic bonding for wafer scale contacting.
Full functionality of this approach is demonstrated with magnetotransport measurements on degenerately doped STM patterned Si:P nanowires up to room temperature, made possible by the use of silicon on insulator substrates.