| AVS 65th International Symposium & Exhibition | |
| 2D Materials Focus Topic | Thursday Sessions |
| Session 2D-ThP |
| Session: | 2D Materials Poster Session |
| Presenter: | José Alexandre Diniz, University of Campinas, Brazil |
| Authors: | F.C. Rufino, University of Campinas, Brazil A.M. Pascon, University of Campinas, Brazil D.G. Larrude, Mackenzie Presbyterian University, Brazil W.C. Mariano, University of Campinas, Brazil J.A. Diniz, University of Campinas, Brazil |
| Correspondent: | Click to Email |
With the need of the development of smaller devices, the search for materials with physical and chemical properties favorable to these advances has become a priority. However, Moore's Law is no longer verified [1], reinforcing research into new technologies, with a strong focus on 2D materials. The graphene, a 2D material, composed of sp2 hybrid carbon atoms, emerges as a strong candidate in nanotechnology applications due to its outstanding electronic properties, high electrical conductivity, mobility, flexibility, mechanical strength and transparency [2], making it the ideal material to replace the silicon in the traditional FETs.
We report the fabrication of transistors based on graphene channel (GraFETs), applying the photolithography and oxygen plasma etching processes to define the graphene channel region, creating ten micro wires, which are parallel connected, at the same device, as FinFET transistors based on silicon nanowires. Usually, the graphene channel region is not formed by the wires in parallel, but by square or rectangular shapes. Devices, with wires in parallel, can get an increase in drain-source current and the transconductance response, which can improve the sensitivity of sensors based on GraFETs. Thus, in this work is presented the fabrication of GraFETs with: i) High quality CVD (Chemical vapour deposition) monolayer graphene, which was transferred on the GraFETs; ii) The channel, with total width of 3.6 µm, was formed by ten micro wires in parallel, with each width of about 0.36 µm, (obtained by lithography and O2 plasma etching).
The Raman spectroscopy was used to investigate the integrity of graphene structure on GraFETs during the fabrication. The Scanning Electron Microscopy (SEM) was used to show the channel formation with ten graphene wires and to measure the dimensions of these wires. The drain-source current versus drain-source voltage, the drain-source current versus gate voltage, and the transconductance versus gate voltage, were extracted to evaluate the electrical characterization of our GraFETs. The graphene used in the manufacture of the transistor was obtained through CVD, where the graphene is grown on a copper substrate by surface catalysis of the CH4 and H2 gases [3]. The growth process is done in a CVD chamber with a vacuum of 10-3 torr and a temperature of 1000 ºC, the transference of CVD monolayer graphene on the device region using wet transfer method and PMMA as a supporting layer [4].
[1]H. N. Khan et al., Nat. Electronics , 14 (2018).
[2]K. S. Novolselov et al, Science 306, 666 (2004).
[3]Xuesong Li, et al., Science 324, 1312 (2009).
[4]L. Jiao et al., Am. Chem. Soc. , 12612 (2008).