AVS 63rd International Symposium & Exhibition
    Thin Film Thursday Sessions
       Session TF1-ThM

Paper TF1-ThM10
Reduction of Extended Defects in SiC Epilayers Grown on 2° Offcut Substrates

Thursday, November 10, 2016, 11:00 am, Room 104E

Session: Control and Modeling of Thin Film Growth and Film Characterization
Presenter: Rachael Myers-Ward, Naval Research Laboratory
Authors: R.L. Myers-Ward, Naval Research Laboratory
N. Mahadik, Naval Research Laboratory
R. Stahlbush, Naval Research Laboratory
P. Klein, Naval Research Laboratory
K.M. Daniels, Naval Research Laboratory
A. Boyd, Naval Research Laboratory
K. Gaskill, Naval Research Laboratory
Correspondent: Click to Email

Silicon carbide is a material of interest for high-voltage and high-power switching device applications. Basal plane dislocations (BPDs) are a major concern for SiC bipolar devices as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes. Many researchers have investigated methods to reduce the BPD density by experimenting with pre-growth treatments, substrate orientation, growth parameters and growth interrupts. This work investigates extended defects, morphology and lifetime in 4H-SiC epilayers grown on substrates offcut 2° toward the [11-20].

Epilayers were grown on 2° offcut substrates in a horizontal hot-wall reactor using the standard chemistry of silane (2% in H2) and propane. Epilayers were grown at various growth rates, C/Si ratios, and growth temperatures. The pressure was maintained at 100 mbar for all growths. Some samples were grown with a 5 µm highly doped n+ buffer layer using ultra high purity nitrogen prior to the low doped epilayers. Ultraviolet photoluminescence (UVPL) imaging was used to identify BPDs in the low doped epilayers. Time resolved photoluminescence measurements were performed to determine the minority carrier lifetime of the layers and Raman spectroscopy was used to analyze polytype inclusions. Electron trap concentrations were determined using deep level transient spectroscopy (DLTS). Surface roughness was measured by atomic force microscopy and the morphology was also characterized using Nomarski microscopy.

When a 15 µm epilayer was grown without a buffer layer, step bunching was observed and the surface roughness was 6.0 nm RMS. For comparison, a standard 4° offcut sample typically has 3.0 nm RMS for a 20 µm epilayer. Using UVPL, it was found that after 4 µm of epi, 90% of the BPDs had converted in the low doped layer as compared to 70% in a 4° offcut sample, indicating the conversion is faster in the lower offcut material. 3C-SiC inclusions were present in the epilayers as verified using Raman spectroscopy for both unintentionally doped (UID) and N+ epilayers. These inclusions were reduced by increasing the growth temperature and lowering the C/Si ratio for N+ epilayers, but increasing C/Si ratios for UID films. Changing these growth parameters resulted in specular film morphology and resulted in minority carrier lifetimes on the order of 1 µs.