Adoption of Atomic Layer Deposition (ALD) for semiconductor manufacturing has more than doubled over the past 3 years driven by inflections in both logic and memory devices from planar to 3D structures requiring conformal deposition and is set to double again over the next 3 to 5 years as the need for continued device scaling is expected to drive the need for unique and differentiated ALD films. The use of Spatial ALD techniques serves as a disruptive means compared to conventional ALD processes to address the needs of this rapidly growing market. Though Spatial ALD is not new, having been used in volume production for solar cells and Roll-to-Roll systems, adapting spatial ALD technology for the semiconductor market where device performance requirements demand a magnitude higher level of film deposition control faces numerous challenges. In this presentation, we will review the hardware challenges associated with adapting spatial ALD technology to high volume semiconductor manufacturing, and our design approach used in developing a new ALD platform to address those challenges.