Paper TF-ThP16
PEALD BSG PSG Doping Diffusion Characterization

Thursday, November 10, 2016, 6:00 pm, Room Hall D

Continuous CMOS scaling becomes more and more difficult due to the extreme process challenges. After FIN FET device architectures were introduced into the industry at end of 2011, they have been widely adopted by the industry to continue device scaling with improved short channel control and performance at lower supply voltages. Compared to SOI substrate, careful punch-through stopper junction design and STI are required for FINs formed on bulk substrate [1]. A novel subfin doping technique had been reported at the 14nm node, which is achieved through solid-source doping to enable better optimization of punch-through stopper dopants [2]. High dopant concentration below the channel to suppress leakage and low dopant concentration in the channel for high performance & less variability can be achieved by solid-source doping techniques while high impurity concentration in the channel and silicon damage could be caused if ion implantation is used for this subfin doping. In this paper, thorough diffusion characterizations were performed at both BSG (Boron Doped Silicate Glass) and PSG (Phosphorus Doped Silicate Glass) on silicon substrates with different drive-in anneal conditions and different insulator cap options. A novel solid-source doping scheme with BSG for NFET subfin doping and PSG for PFET subfin doping is proposed due to the fact that no enough space exists to continue the traditional dual doped liner (BSG/PSG) scheme on 7nm node and beyond.

[1] K. -I. Seo et al., “A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI” Symp. VLSI Tech. Dig., p.14 – 15, 2014

[2] S. Natarajan et al., “A 14nm Logic Technology Featuring 2nd-Generation FinFET , Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588 m2 SRAM cell size” IEDM. Tech. Dig, p.71 – 73, 2014