Cu metallization has been used for back end of the line (BEOL) on-chip interconnections since 1997. However, scaling Cu BEOL dimensions has increased Cu resistivity and degraded electromigration (EM) reliability. The Cu effective resistance has increased rapidly as the interconnect size has reduced and the ratio of liner area to total interconnect cross sectional area has increased. This size effect was caused primarily by increasing the probability of electron scattering with interfaces and grain boundaries. The EM lifetime degradation was caused by an increase in the volume fractions of diffusing atoms at interfaces and grain boundaries and a decrease in the void volume required to cause EM failure. It is estimated that ~ 70% of interconnect metal area could be occupied by the liner in the 5 nm technology node for reliable Cu metallization. To this end, an alternate metal, Co, was investigated. Multi-level Co BEOL was fabricated using typical 10 nm node technology wafer processing steps. A Co dual damascene process was used to fill the interconnect trenches and holes. The present Co resistivity study showed a similar size effect in Co as in Cu. This can be explained by the fact that the slope of resistivity vs. interconnect size is proportional to the product of the electron mean free path and resistivity, with the two slopes being about the same for Cu and Co. The effective resistivity difference between Co and Cu becomes small when no liner is used in Co lines. EM in 22 nm to 88 nm wide Co lines was tested using sample temperatures from 376^oC to 425^oC. Two–level EM structures consisted of either Co M1 to Co V1 to Co M2 or W CA to Co V0 to Co M1. The EM stress conditions for Co were far more severe than those for Cu. For comparison, EM in 24 nm wide Cu lines with a Co cap was also included. These data showed that both Co and Cu BEOL were highly reliable EM.

This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities