| AVS 63rd International Symposium & Exhibition | |
| Surface Science | Wednesday Sessions |
| Session SS+AS+EM-WeA |
| Session: | Semiconductor Surfaces and Interfaces |
| Presenter: | Tedi Kujofsa, University of Connecticut |
| Authors: | T. Kujofsa, University of Connecticut J.E. Ayers, University of Connecticut |
| Correspondent: | Click to Email |
Understanding lattice relaxation and dislocation dynamics has important implications in the design of highly functional and reliable semiconductor device heterostructures. Strain-layer-superlattices (SLSs) have been commonly used as dislocation filters whereby threading dislocations (TDs) can be removed by the insertion of a series of mismatched interfaces. The reduction of the threading dislocation in SLSs can be explained by the bending over of TDs associated with misfit segments of one sense by misfit dislocations having the opposite sense. Furthermore, the use of multilayered metamorphic buffer layers (MBLs) with intentionally mismatched interfaces may be used to take advantage of the strain compensation mechanism.
Previously, we developed a generalized energy minimization model, which determines the equilibrium configuration of an arbitrary compositionally-graded or multilayered heterostructure. The present work focuses on the development of a novel electrical circuit model for understanding equilibrium lattice relaxation in InGaAs/GaAs (001) strained-layer-superlattice heterostructures. This work focuses on the design of the SLS buffer layer of InxGa1-xAs deposited on a GaAs (001) substrate. The SL contains a set of 10 uniform layers with alternating mismatch. In other words, the SSL contains alternating uniform layers of InxGa1-xAs with indium compositions x and x + ∆x respectively. For each structure, we present minimum energy calculations and show that for a given SLS total layer thickness hSLS, it is possible to find the combination x and ∆x such that it provides tight control of the in-plane strain of the strained-layer-superlattice. In addition, for each structure type we present minimum energy calculations by studying the (i) depth profile of strain and (ii) the misfit dislocation density profile. Most importantly, the use of the electrical circuit model allows the analysis of semiconductor heterostructures using a standard SPICE circuit simulator and provides an intuitive understanding of the relaxation process in these multilayered heterostructures.