Invited Paper MS+AS-TuM3
High Volume Materials Characterization in the CMOS Industry

Tuesday, November 8, 2016, 8:40 am, Room 103A

In no time in the past has Materials Characterization been as pivotal to CMOS device R&D as it is today. This stems primarily from the fact that since the era of Denard scaling (shrinkage alone), new materials/ structures have had to be introduced in order for logic devices to continue to adhere to the dimension shrinkage implied by Moore’s law (examples lie in the introduction of strain engineering (introduced in 90nm devices rolled out in 2003), HKMG structures (introduced in 45nm devices rolled out in 2007), and 3D structures (introduced in 22nm devices rolled out in 2011)). This timeline also begs the question: Are we not at the precipice of the next innovation? What is certain is that the CMOS industry will experience significant and in some cases unforeseen changes over the next 2 decades.

Materials characterization is not only needed to support R&D efforts, but is also required to provide insight into manufacturing issues, along with the qualification of a) new fabrication processes, b) new process equipment, and c) process equipment coming off preventative maintenance cycles. Paramount in these areas is analytical precision, repeatability, data quality and speed (turn around time). This stems from the other aspect of Moore’s law; that being that the cost associated with the development/implementation of a new device node must remain financially attractive. Topics covered in this presentation include: the support requirements of a high volume CMOS manufacturing site, merits of academia versus industrial labs, financial justifications of onsite lab/s, along with some recent analytical examples/capabilities.