AVS 63rd International Symposium & Exhibition
    Applied Surface Science Thursday Sessions
       Session AS+SS-ThM

Paper AS+SS-ThM1
Pushing the Limits of Bonded Multi-Wafer Stack Heights while Maintaining High Precision Alignment

Thursday, November 10, 2016, 8:00 am, Room 101B

Session: Depth Profiling, Buried Interfaces, and 3D Analyses
Presenter: Alireza Narimannezhad, Washington State University
Authors: A. Narimannezhad, Washington State University
J. Jennings, Washington State University
M.H. Weber, Washington State University
K.G. Lynn, Washington State University
Correspondent: Click to Email
The last decade in advanced microelectronics has shown great interest in three-dimensional architectures, which was paved by multi-wafer alignment technologies. However, many limitations remain in the fabrication of ultratall stacks as the alignment becomes more challenging and very costly. In this paper, a new cost-effective alignment technique was employed using a set of sapphire rods in through-wafer holes. Cross-sectional analysis, edge profilometry, and electron transmission tests showed ~2 µm alignment tolerances over 1 cm and ~4 µm over 10 cm tall stacks. An off-angle gold sputtering method was developed to fully coat vias of 5:1 aspect before bonding. Also, a new Stamping technique is introduced to coat the vias to a desired height where necessary. In this study, parallel microtubes with aspect ratios of 1,000:1 were formed by aligning ~200 wafers, each including 20,000 gold-coated vias for storing charged particles.