Paper PS-TuM6
Advanced Plasma Etch Techniques for Sub-50nm Pitch Contact & Interconnect Etches

Tuesday, October 20, 2015, 9:40 am, Room 210B

As the semiconductor industry drives into sub-50nm pitches, EUV patterning as well as SADP and SAQP techniques are being explored as means to achieve the desired CDs and pitches needed. EUV patterning is attractive for enabling direct patterning and in principle, is significantly less complicated than SADP, let alone SAQP. However, EUV patterning comes with its own set of challenges, such as softer and thinner resists relative to optical 193nm resists. Also, to date, EUV resists have exhibited more LER/LWR than optical 193nm resists. Finally, the smaller features and pitches are resulting in the reoccurrence of old scaling issues such as RIE lag and pattern collapse. Many of these challenges are being met with innovative plasma etch techniques.

In this paper we discuss the theory behind many of the techniques used to solve the afore mentioned challenges associated with EUV and sub-50nm pitch patterning. In particular, RF pulsing and Bias pulsing are used to increase EUV resist selectivity, reduce LER/LWR, avoid pattern collapse and improve RIE lag in the dielectric etch. In addition we will also discuss the theory and application of AMMP (Advanced mixed mode pulsing) to improve the corner selectivity of low-k spacer in MOL to allow for the generation of self-aligned contacts. Finally, AMMP techniques were used to mitigate feature to feature CD variation incoming from litho.

This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.