AVS 62nd International Symposium & Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS+EM-MoA

Paper PS+EM-MoA4
Plasma Etching of Directed Self Assembly based Patterns for Aggressively Scaled CMOS Applications

Monday, October 19, 2015, 3:20 pm, Room 210B

Session: Directed Self Assembly and Plasma Synthesis of Novel Materials
Presenter: Hiroyuki Miyazoe, IBM T.J. Watson Research Center
Authors: H. Miyazoe, IBM T.J. Watson Research Center
H. Tsai, IBM T.J. Watson Research Center
R.L. Bruce, IBM T.J. Watson Research Center
S.U. Engelmann, IBM T.J. Watson Research Center
M. Brink, IBM T.J. Watson Research Center
A. Pyzyna, IBM T.J. Watson Research Center
C. Liu, IBM Albany Nanotech Center
A. Vora, IBM Almaden Research Center
D. Sanders, IBM Almaden Research Center
M. Maher, The University of Texas at Austin
W. Durand, The University of Texas at Austin
C. Ellison, The University of Texas at Austin
G. Willson, The University of Texas at Austin
M. Guillorn, IBM T.J. Watson Research Center
E.A. Joseph, IBM T.J. Watson Research Center
Correspondent: Click to Email
As the feature size in CMOS technology continues to shrink, patterning below 30 nm pitch faces many challenges. Directed self-assembly (DSA) [1] and sidewall image transfer (SIT) [2] patterning techniques can augment conventional lithographic patterning by providing sublithographic multiplication of feature pitch. Recently, our group successfully demonstrated the electrical characterization of FinFET devices comprising fins formed by DSA of poly (styrene-block-methyl methacrylate) (PS-b-PMMA) block copolymers (BCPs) at 28nm fin pitch [3]. In addition, we demonstrated copper lines with dielectric patterns formed by DSA at 28nm pitch followed by metallization [4]. Patterning of Si, SiNx and SiOx at a ~24 nm feature pitch using PS-b-PMMA BCP was also shown [3]. In this work, we discuss a parametric study of factors impacting fine feature patterning to further optimize DSA line-space patterning using PS-PMMA BCPs at 28 and 24nm pitch, and high chi BCP at 20nm and 18.7nm pitch. The use of templated DSA to generate line-space structures in the aforementioned materials was used to investigate the control of critical dimension (CD), line edge roughness (LER) and line width roughness throughout the patterning process. The line roughness of the hardmask becomes smaller at the lower substrate temperature during etch. The CD of lines was controlled well between 11nm and 15nm at 28nm pitch by controlling the etching time while keeping the LER constant (at ~3nm). We also confirmed that O2-free plasma gas chemistry is more advantageous for BCP patterning in case of organic-organic polymer. These initial patterning studies may play an important role in understanding feature formation and density limiting ground rules.

[1] J. Cheng et al., SPIE 2010, [2] H. Yaegashi. SPIE 2012, [3] Tsai, IEDM 2014, [4] Pyzyna VLSI 2015