AVS 62nd International Symposium & Exhibition
    Plasma Science and Technology Wednesday Sessions
       Session PS+AS+SS-WeA

Paper PS+AS+SS-WeA10
Role of Plasma Density in Damage Characterization and its Impact on Low-Damage Plasma Process Design

Wednesday, October 21, 2015, 5:20 pm, Room 210B

Session: Plasma Surface Interactions
Presenter: Koji Eriguchi, Kyoto University, Japan
Authors: K. Eriguchi, Kyoto University, Japan
M. Kamei, Kyoto University, Japan
Y. Nakakubo, Kyoto University, Japan
K. Ono, Kyoto University, Japan
Correspondent: Click to Email

Plasma process-induced damage (PID) is one of critical issues in designing metal−oxide−semiconductor field-effect transistors (MOSFETs) with higher performance and reliability. The damage creation mechanisms—plasma-induced physical damage (PPD) and charging damage (PCD) [1]—have been characterized by various techniques so far [2] to design low plasma processes. In this study, conflicting results leading to erroneous conclusions in designing future plasma processes are presented, where ion flux and charge injection from plasma (~ plasma density) play a key role in these conventional characterizations. Firstly, regarding PPD, n-type (100) Si wafers were exposed to Ar-based ICP and CCP discharges [3] and the localized defects were created in the Si substrates by ion bombardment. It is found that, although the average energy of incident ions (Eion) is larger for the case of CCP, the latent defect density (ndam) of CCP-damaged samples is smaller than that of ICP, even after the damaged-layer removal. This observation is in sharp contrast to previous pictures, i.e., the larger Eion leads to the larger PPD. Secondary, MOSFETs with "high-k" (HfSiOx) gate dielectric were damaged by the Ar-based ICP plasma and the high-k damage (~ carrier trap site generation) by PCD is evaluated by time-dependent dielectric breakdown (TDDB) measurement [4]. We identify that the TDDB lifetime becomes longer under a certain amount of charge injection by plasma-induced current. This finding implies that one might be misled to an erroneous design rule of future LSIs. We propose a model explaining these conflicting results, where both ion flux and charge injection from plasma and the nature of the analysis techniques are taken into account. Since modern FinFETs with high-k dielectrics [5] are susceptible to PPD and PCD, the present model should be intensively implemented in designing future "low-damage" plasma processes.

This work was supported in part by a Grant-in-Aid for Scientific Research (B) 25630293 from the Japan Society for the Promotion of Science.

[1] For example, K. Eriguchi and K. Ono, J. Phys. D 41, 024002 (2008).

[2] M. Fukasawa et al., Dry Process Symposium, 183, (2013).

[3] Y. Nakakubo et al., ECS J. Solid State Sci. Technol., 4 N5077 (2015).

[4] M. Kamei et al., IEEE Int. Integrated Reliability Workshop Final Report, 43 (2014).

[5] For example, I. Ferain et al., Nature 479, 310 (2011).