| AVS 61st International Symposium & Exhibition | |
| Thin Film | Thursday Sessions |
| Session TF-ThP |
| Session: | Thin Films Poster Session |
| Presenter: | David Mateos, University of Campinas, Brazil |
| Authors: | D. Mateos, University of Campinas, Brazil J.A. Diniz, University of Campinas, Brazil S.N. Mestanza Muñoz, Federal University of ABC, Brazil N. Nedev, Autonomous University of Baja California, Mexico M.A. Curiel Alvarez, Autonomous University of Baja California, Mexico M. Mederos Vidal, Federal University of ABC, Brazil B. Valdez, Autonomous University of Baja California, Mexico G. Montero, Autonomous University of Baja California, Mexico |
| Correspondent: | Click to Email |
In this work we present results for two types of thin films deposited by ECR–CVD: silicon oxide (SiO2) and hydrogenated amorphous silicon (a–Si:H) with thicknesses of about 6–8nm and 3–4nm respectively. SiO2/a–Si:H and SiO2/a–Si:H/SiO2 structures for potential application in Non–Volatile Memories, were deposited on p–type (100) c–Si wafers under the following conditions: a gas pressure of 2.0mTorr, an applied ECR microwave (frequency of 2.45GHz) with power of 250Watts and a substrate temperature of 20°C. The precursor gases used for SiO2 deposition were 2% of SiH4 diluted in Ar, Ar and O2 with flows of 125, 5 and 2.5sccm, respectively. The a–Si:H layers were deposited without oxygen using the same SiH4 and Ar flows. The films were subjected to furnace annealing in N2 at temperatures in the 800–1100°C range for 60min. Different oxygen and silicon incorporation into the films were extracted using Energy Dispersive X–ray (EDX) analysis (Fig1). Information for the layer thicknesses and optical properties was carried out by Single Wavelength Ellipsometry (SWE) λ~638nm. The thickness measured was 7–11nm and 9–20nm for two and three layers, respectively. Refractive index (n) values between 1.46–1.53 that were obtained are greater than stoichiometric silicon oxide (n=1.457) reported in the literature, indicating formation of thin films rich in silicon. MOS capacitors were fabricated by r.f. sputtering of Al as top (d~0.5 µm) and back contacts. These capacitors were sintered at 450°C in forming gas (92%N2 and 8%H2) for 5, 10 and 20min. Electrical characterization was carried out by Capacitance–Voltage (C-V) measurements. The increase of the low temperature annealing time, leads to an improvement of the SiO2/Si interface seen as an increase of the slope of the high frequency C–V dependence. The capacitance variation in accumulation (Cacc) is in the range of 160–180pF for two layer capacitors which correspond to a thickness of 6–7nm (Fig2). In the same way for three layers the variation of Cacc is larger and the thickness calculated is 11–17nm (Fig3). The obtained values are in agreement with the expected thickness determined by SWE. Three–layer MOS capacitors annealing in forming gas for 20min showed hysteresis in their C–V measurements with ramps varying from negative to positive voltages and back. The flat–band Voltage shift (ΔVFB) obtained for capacitors annealed at 800°C and 1000°C were: -2.7V to -2.13V and -4.3V to -2.48V showing an hysteresis window of 0.57V and 1.82V, respectively (Fig4). By the other hand for two–region structures do not present hysteresis (Fig5) which means that three-layer structures could be a possible application as memory devices.