| AVS 61st International Symposium & Exhibition | |
| Plasma Science and Technology | Thursday Sessions |
| Session PS1+TF-ThM |
| Session: | Plasma Deposition and Plasma Assisted ALD |
| Presenter: | Yuanxia Zheng, Penn State University |
| Authors: | YX. Zheng, Penn State University G.B. Rayner, Kurt J. Lesker Company A. Agrawal, Penn State University S. Datta, Penn State University R. Engel-Herbert, Penn State University |
| Correspondent: | Click to Email |
The development of Ge-based field effect devices requires the integration of a high quality dielectric that forms an electrically well behaved semiconductor dielectric interface. Although GeO2/Ge has been found promising, the thermodynamic instability as well as the relatively low dielectric constant of GeO2 requires an alternative approach. The utilization of an ultrathin Si layer to move the semiconductor/dielectric interface from Ge into Si has been successfully demonstrated; however, the introduction of a planar thin layer into the gate stack is incompatible with a 3D FinFET manufacturing process flow. It is thus desirable to develop a multilayer gate stack by atomic layer deposition process, where an ultrathin GeO2 layer can be thermodynamically stabilized and combined with a high-k dielectric film to meet the stringent requirement of low interface trap density and large capacitance density while maintaining a low gate leakage.
In this talk, we will present an approach of developing a multilayer gate-stack of HfO2/Al2O3/GeO2 for Ge using in-situ processing control in plasma-enhanced atomic layer deposition (PEALD) by utilizing real-time monitoring capabilities of in-situ spectroscopic ellipsometry (SE). Pristine Ge-surface is obtained by removing native GeOx using H-plasma and an ultrathin GeO2 layer is grown thereafter by O-plasma anneal; in-situ SE is used to monitor the process and to control GeO2 thickness. An ultrathin bilayer of alumina and hafnia is subsequently grown using thermal ALD and large capacitance densities with equivalent oxide thicknesses (EOT) below 1 nm and gate leakages below 1×10-4A/cm2 at -1V (EOT=0.7 nm) are demonstrated. The impact of the thickness of the individual dielectric layers on interface trap density, determined by the conductance and the Terman method, leakage current and EOT is discussed. We will further discuss how in-situ SE is used to optimize process-relevant parameters for native oxide etching, intentional oxidation and deposition of high-k dielectrics. The potential of this in-situ real-time process metrology is projected for the development of high quality high-k dielectrics on other high mobility low band gap semiconductor materials.