Paper PS-TuM3
Contact Resistance Degradation Caused By Plasma Charging of Silicon on Insulator During Contact Etch

Tuesday, November 11, 2014, 8:40 am, Room 308

Contact formation is of enduring importance to integrated circuit manufacturing. A typical contact etch process uses fluorocarbon plasmas to etch small diameter, high aspect ratio holes through deposited silicon dioxide, landing on silicide. Contact etch processes provide high etch rate selectivity due to fluorocarbon polymer deposition on non-oxide surfaces. This selectivity is necessary for bi-level contacts landed on gates and active Si but the interactions among etching, deposition, and the structures being formed are complex and given to non-obvious failure modes. In this presentation we report on the characterization of a failure mode in which contacts to device Si on silicon-on-insulator (SOI) wafers form voids between the interconnect plug and the underlying silicide after thermal stress. The initial parametric signature was an increase in contact resistance for Kelvin structures of a specific design. From a nominal resistance of 2.5Ω, resistance increases by a factor of 3 were common. Through destructive physical analysis we correlated the increase in Kelvin resistance to the formation of small voids at the base of the Kelvin contact. We developed the following model to describe the condition that leads to the voids. As the contact etch reaches the Si surface, the potential at the bottom of the hole shifts abruptly from equilibrium, balancing electron and ion currents, to a more positive potential. This positive potential suppresses ion bombardment at the base of the contact, reducing etch rate and allowing more fluorocarbon polymer to accumulate. Electron current to the bottom of the hole increases to equilibrate the disturbed potential, but is limited by electron shadowing and the available contact hole area. The duration of the excess positive potential is proportional to the specific capacitance of the revealed Si surface, which, for islands on SOI wafers with shallow trench isolation, may be thousands of times larger than an equivalent bulk wafer. Smaller contact area (i.e. fewer contact holes) in a single island exacerbates the transient potential duration and the resulting etch process disturbance. We developed test structures and executed experiments to explore the transient potential concept and the local Si capacitance relative to the open contact area. Without adequate mitigation, the accumlated polymer leads to a weakened interconnect interface that is vulnerable to voiding and delamination.

Sandia is a multiprogram laboratory managed and operated by Sandia Corporation, a Lockheed Martin Corporation, for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.