| AVS 61st International Symposium & Exhibition | |
| Plasma Science and Technology | Monday Sessions |
| Session PS-MoM |
| Session: | Current Challenges of Plasma Etching Technologies |
| Presenter: | Emmanuel Dupuy, CNRS-LTM, France |
| Authors: | E. Dupuy, CNRS-LTM, France M. Fouchier, CNRS-LTM, France E. Pargon, CNRS-LTM, France J. Pradelles, CEA-Léti, France H. Grampeix, CEA-LETI, France P. Pimenta-Barros, CEA, LETI, France S. Barnola, CEA, LETI, France O. Joubert, LTM - CEA/LETI, France |
| Correspondent: | Click to Email |
Line width roughness (LWR) or line edge roughness (LER) is considered today by the microelectronic industry as a critical factor limiting CMOS transistors downscaling. According to the international technology roadmap for semiconductors, LWR and LER values must be controlled below 2 nm for the next sub-20 nm nodes, which remain a technological challenge for all nanopatterning options and metrology tools. Understanding and minimizing LER at this nanometer scale thus requires an accurate and insightful characterization of the sidewall roughness.
Among advanced nanopatterning solutions, spacer patterning has emerged as a reliable and competitive technique to fabricate fine patterns down to 10 nm. This technique consists in depositing a spacer material on each side of a core (mandrel) defined by lithography and then removing the core to halve the pitch. One critical aspect of this approach is the control of the LER since the spacer patterns are asymmetric from their formation. The right and left sides of the spacer are not obtained by the same technological step and could lead to different LER values on the left and right sidewalls. This behaviour could be problematic if this asymmetry is transferred to the final pattern.
In this work, we propose to characterize and evaluate finely the LWR/LER evolution after each technological step involved in a resist-core spacer patterning process targeting a half-pitch of 20 nm and 10 nm. In this particular case, spacers are directly deposited on the side of the resist. Advantages are less processing steps, a simplified stack and a reduced production cost. A method based on a power spectral density (PSD) analysis is used take into account the noise level of CDSEM images in the LWR/LER estimation of these fine patterns. A full description of the sidewall roughness including its spatial frequency distribution is obtained at each step with an estimation of noise-free parameters such as roughness amplitude (3Ợ ), correlation length (ξ), and roughness exponent (α).” For the 20 nm node, LWR and LER values are drastically reduced to 2.5nm and 2.2nm respectively. The correlation length is found to range from 8 to 22 nm and the roughness exponent from 0.4 to 0.9 for the final silicon lines. Results for the 10 nm node will be discussed in view of evaluating and optimizing process performances.