| AVS 61st International Symposium & Exhibition | |
| Plasma Science and Technology | Monday Sessions |
| Session PS-MoM |
| Session: | Current Challenges of Plasma Etching Technologies |
| Presenter: | Masanobu Honda, Tokyo Electron Miyagi Limited, Japan |
| Correspondent: | Click to Email |
For 7nm and beyond VLSI nano fabrication, fine process control in the order of nm or less is required, current incremental techniques may not address the challenges for future nano fabrication. In the High Aspect ratio processing such as 3DNAND and DRAM capacitor, miniaturization of the feature dimensions adds challenges to ion-radical transportation to the bottom of the feature, further aggravating etch yield and etch linearity. Further, in Logic MOL SAC, trade-off between the etch linearity and substrate recesses reduction are increasingly being focused. On the other hand, for BEOL interconnects, achievement of within-wafer uniformity of nm or less, and defect reduction at fine-node are added challenges. We have continued to challenge a variety of these dielectric etch issues, in order to provide technical solutions to enable future devices.
With further lithography related challenges and delays, complexity in patterning increases etch related challenges, continuous processing of the multilayer film with high accuracy corresponding to the multi-pattern is required. ARDE, reducing line roughness (LER/LWR), Trim, Hole Shrink and countermeasures in accordance with the thinning of the EUV resist are important challenges that etch has to overcome. We have effectively overcome these problems using unique resist treatment technologies based on high-speed electron beam and a sidewall protection film using DC super-imposed RF plasma system [1,2]. However, we still encounter trade-off when solving these challenges, it is necessary to overcome the trade-off by introducing a new concept to enable further miniaturization.
As noted above, there are many challenges and potential tradeoffs to arrive at an optimal solution; we need a breakthrough to overcome these challenges. We have continued to explore and innovate solutions, as a result we are honing on a possible solution integrating etch and ALD techniques. Establishing this Etch-ALD concept and developing a robust flow will be a major breakthrough in overcoming patterning and other critical level issues related to nano-feature processing dielectrics and to sustain the Moore's Law.
Reference
[1] M. Honda et al., AVS 60th Int. Symp. & Exhibit. (2013)
[2] M. Honda et al., Proc. of SPIE 8328-09 (2012)