Paper PS-MoA8
Challenges of 3D NAND Staircase Patterning Process

Monday, November 10, 2014, 4:20 pm, Room 308

NAND memory microfabrication is at the transition point to vertical structures. A variety of 3D NAND device designs have been reported, such as bit cost scalable (BiCS) and terabit cell array transistor (TCAT). Despite the difference in the structures and operational mechanisms of 3D NAND devices, the microfabrication processes share a common first step, the formation of the landing pads for the control gate via contacts. The “staircase” of pad landings is realized by alternating film etching and resist trimming. To ensure high yield, the registration for the vias must be ensured by the insitu staircase patterning process with CD uniformity being the most critical figure of merit for desired yield. CD uniformity is most sensitive to the resist trimming process and is controlled by plasma distribution and electrostatic chuck temperatures. Local CD non-uniformity may originate from microloading effect or asymmetry impact, and the approaches to improve the local CD uniformity focus on mitigating loading and reducing the asymmetry with process and hardware development, that are also supported by quantitative modeling results. Early versions of the staircase patterning process resulted in low throughput due to multiple resist trimming steps. High throughput is required to reduce the cost of fabrication. Power, flow, and pressure are effective knobs in improving the resist trimming rate. Reducing the gas transition time and using continuous plasma between different gas has also proven effective for further improving throughput. Challenges and progress for 3D NAND staircase patterning process will be discussed, and innovative hardware and process solutions will also be presented.