AVS 61st International Symposium & Exhibition | |
Plasma Science and Technology | Monday Sessions |
Session PS-MoA |
Session: | Advanced FEOL/Gate Etching |
Presenter: | Vahid Vahedi, Lam Research Corp |
Authors: | V. Vahedi, Lam Research Corp J. Marks, Lam Research Corp |
Correspondent: | Click to Email |
Plasma etch plays a key role in obtaining structural fidelity in all three dimensions. Precision is obtained by means of wafer- to- wafer, chamber- to- chamber and tool- to- tool matching. Accuracy on the other hand requires control of proximity and 3D effects such as critical dimension (CD) loading, profile loading, aspect ratio dependent etching (ARDE), and selectivity.
As we approach devices with a half pitch of 10 nm and below, atomic scale fidelity is required because the device dimensions and their allowed tolerances are of the same order of magnitude as the inter-atomic distances in the crystal lattice. This type of performance can be obtained when the material is removed layer by layer. The etch process is comprised of single unit steps which repeat in cycles. Each step uses the simplest possible chemistry to surgically target specific reactions at the wafer surface such as activation, removal, and passivation. We call this layer- by- layer etch with atomic fidelity Atomic Layer Etchatomic layer etch1.
In this presentation, we introduce the framework of high productivity, production- worthy ALE atomic layer etch and the implications for hardware and process development. Results for both dielectric and conductor etch obtained with Lam’s Research’ latest etch products will be presented.
References:
1. Kanarik, et al., Solid State Technology, (2013) 14-17.