Plasma etching is the ubiquitous method for high-resolution pattern transfer in semiconductor and related technologies. As lithographic techniques advance towards 5 nm half-pitch for applications in storage media, nanoelectronics, and plasmonic based devices, plasma etching processes must follow suit. This brings enormous and arguably insurmountable challenges using typical plasma hardware. For instance, very high etching selectivity must be achieved to accommodate mask heights (~1-2 times the feature size) which must shrink to mitigate pattern collapse in the lithographic and etching steps. In addition, line edge roughness at down to sub 1 nm levels must be achieved. To meet these enormous challenges we are investigating etching processes with temperatures down to -140 °C. Low temperature etching was first introduced by Tachi.¹ Lower etching temperatures can bring benefits such as higher selectivity processes, larger process windows, and reduced plasma damage which will be important for achieving sub-5 nm features.

We will discuss nanoscale cryogenic etching work in silicon, chromium, and silicon dioxide. With careful micron and deep nanoscale etching we show that cryogenic temperature etching of silicon, previously studied in great detail at the micron scale, ^2,3 can provide extreme selectivity and anisotropy at the nanoscale even with soft masks derived from block copolymer lithography. Selectivity is enhanced while maintaining pattern verticality because resist etch rates decrease as temperature is lowered. Changing to a chromium hardmask increases selectivity towards deeper sub-10 nm features at 20:1 aspect ratios. Studies of chromium etching show a temperature dependent etch rate that can be used to enhance profile control and limit mask undercut, necessary when nanometer controlled is required. Finally, we will discuss investigations into reduced temperature silicon dioxide etching for applications in patterned media and vertical NAND.