Invited Paper EM2-ThM3
Physical Mechanisms and Scaling of the Resistive Memory (ReRAM)

Thursday, November 13, 2014, 8:40 am, Room 314

The resistive memory (ReRAM) is attracting strong interest from the industry and academia for its low-power, high-speed and nonvolatile behavior. ReRAM properties are compatible with many of the requirements of storage (e.g., the solid state drive, or SSD) and memory (e.g., SRAM or DRAM), thus ReRAM may potentially revolutionize computing architectures in the future. While ReRAM has been recently introduced in the ITRS, the industrial programs for device development, volume production and commercial exploitation are still challenged by the lack of understanding about device physics, reliability and scaling.

This work will discuss the recent progress on the understanding of ReRAM physics. First, a numerical model for ReRAM switching will be described, highlighting the primary role of defect migration driven by Joule heating and electric field. The model will be tested under several conditions of voltage and currents, showing the model capability to identify new operation modes for self-select ReRAM and enhanced multilevel operation. Finally, the scaling issues will be addressed, explaining the device variability data with the aid of a Monte Carlo model for discrete defect migration. The fundamental tradeoff between power reduction and device reliability will be finally discussed.