Paper EM+2D-TuA12
Reliability of nc-CdSe Embedded ZrHfO High-k Dielectric Nonvolatile Memory – Temperature Effects

Tuesday, November 11, 2014, 6:00 pm, Room 314

Previously, it was reported that by adding the third element into the high-k film, the bulk and interface material and electrical properties can be improved [1]. For example, the Zr-doped HfO₂ film (ZrHfO) shows the higher crystallization temperature, a lower interface state density, and a larger effective k value than those of the un-doped HfO₂ film [1,2]. Furthermore, nanocrystals have been embedded into this kind of high-k film for the nonvolatile memory (NVM) application to replace the conventional floating-gate flash memory due to the improved device characteristics and reliability [3]. The nanocrystalline cadmium selenide (nc-CdSe) embedded ZrHfO MOS capacitor has shown excellent charge trapping and retention capabilities [4]. However, most studies on the nanocrystals embedded high-k memory devices are done at the room temperature. Since the temperature in the high density integrated circuit can be much higher than room temperature, it is imperative to study the reliability at a raised temperature [5]. In this paper, the temperature effects on memory functions were investigated on the nc-CdSe embedded sample in the range of 2 0^oC to 120^oC. Compared with the fresh C-V curve, the flat band voltage (V_FB) of C-V curve shifts to the negative or positive gate voltage (V_g) direction after being stressed at -6 V or +6 V for 10 s, respectively. With the increase of the temperature, the magnitude of the V_FB shift increases at -6 V stress but decreases at +6 V stress. With the increase of the temperature, the hole-trapping is enhanced due to the increase of injection and retention of holes to the trapping sites. However, at the high temperature, electrons are possibly transferred through the whole high-k stack with minimum trapping to the high-k stack. In addition, at the high temperature, the nc-CdSe embedded sample has the large relax current with the high discharge rate due to the increasing release of the trapped charges with large thermal energy. The charge retention capability of the device decreases with the increase of the temperature. For example, the device stressed at -6 V for 20 s will retain 30% of the original trapped holes at 20^oC, 23% at 70^oC, and 15% at 120^oC, respectively, after 10 years. This is because the stored charges gain the high thermal energy and the bulk high-k film is more conductive at the high temperature.