Deposited high-k dielectrics with metal gates have replaced SiON gate with poly electrodes for several Logic nodes and rapidly followed with integration changes from planar to 3D FINFET structures. Performance is no longer through just scaling, and next generation devices have gaps that are being addressed with channel engineering using high mobility materials such as SiGe, Ge and III-V compound semiconductors. Gate stacks now involve several thin films of dissimilar material whose interfaces need to be precisely controlled as well as being conformal around the fin and between the spacers. The stack usually involves the channel material followed by a thin interface layer(iL), high-k dielectric and metal gate cap(MG cap) and each layer range from 0.5 to 2nm. In addition several layers may need plasma or thermal treatment to improve reliability and BTI of the gate stack. To understand performance of these stacks, XPS has been applied to compliment device results. In Fab XPS is a powerful tool to provide in short time information on stack thickness, composition and changes in bonding. Examples will be given to show how XPS has been used to optimize and compare high-k stack on Si, SiGe and Ge. In addition iL/high-k/TiN cap has been studied and further examples given and related to electrical device results.