| AVS 60th International Symposium and Exhibition | |
| Plasma Science and Technology | Tuesday Sessions |
| Session PS2-TuM |
| Session: | Advanced FEOL/Gate Etching |
| Presenter: | P. Friddle, Lam Research Corp |
| Authors: | S. Mignot, GLOBALFOUNDRIES U.S. Inc. I.C. Estrada-Raygoza, IBM H. He, IBM K. Akarvardar, GLOBALFOUNDRIES U.S. Inc. J. Cantone, GLOBALFOUNDRIES U.S. Inc. B. Doris, IBM A. Jacob, GLOBALFOUNDRIES U.S. Inc. S. Schmitz, Lam Research Corp J. Lee, Lam Research Corp P. Friddle, Lam Research Corp M. Goss, Lam Research Corp |
| Correspondent: | Click to Email |
FinFET device enables scaling of CMOS technology due to its reduced short-channel effects. Realization of this potential is highly dependent on achieving ideal fin structure shape and reducing variability at the front-end of the process. In particular, fin width and high uniformity are critical. The width of the fin structure is typically required to be at a critical dimension that is below resolution limit of single exposure conventional 193nm immersion lithography (i.e, <40nm half pitch). Over the last couple of technology nodes one common technique for fin formation at tight pitch is to use patterning process flow of Sidewall Image Transfer (SIT).
In this publication, a Double Sidewall Image Transfer (SIT2) etch patterning process has been demonstrated for sub 40nm pitch at fin step. The SIT2 process scheme that has been explored includes silicon mandrel etch followed by Nitride Spacer deposition and etch. Process integration at this level requires a process free of collapsing features and with minimum pitch variations. SIT2 main etch challenges will be reviewed. Etch process mechanisms both physical and chemical have been investigated to achieve silicon etch fin pattern and selectivity to the hard mask and spacer materials as well as uniformity for both macro-to-macro and across wafer.
This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.