Invited Paper PS2-TuM3
Metrology and Linewidth Roughness Issues during Complex High-k/Metal Gate Stack Patterning for sub-20nm Technological Nodes

Tuesday, October 29, 2013, 8:40 am, Room 104 C

Gate Line Width Roughness (LWR) or Line Edge Roughness (LER) is considered today as a factor limiting CMOS downscaling. No technological solution is currently known to reach the 1.7nm gate LWR required for the sub-20nm technological node. The origin of the LWR/LER of the final transistor gate is mainly attributed to the significant roughness of the photoresist (PR) pattern printed by the lithography step, which is partially transferred into the gate stack during the subsequent plasma etching steps. Thus, those passed few years, many efforts have been focused on the development of post-lithography resist treatments in order to minimize the LWR of resist patterns prior to plasma transfer. Another issue related to LWR/LER is the availability of accurate and convenient metrology tools for their evaluation. The status on LER/LWR metrology is that there is today no reliable and efficient metrology equipment to determine LWR at the very bottom of structures, where the key LWR information lies, as well as to estimate sidewall roughness of complex high-k/metal gate stacks composed of a multitude of very thin layers of dielectrics, metals and semiconductors.

We first propose a method based on AFM to measure LER accurately down to feature bottom for any types of pattern profiles (anisotropic, tapered or re-entrant). We will show that it presents a great potential for better understanding the mechanism of LER transfer during complex high-k/metal gate stack patterning.

Various post-lithography processes based on thermal or plasma treatments are also evaluated to decrease resist pattern LWR. A particular attention is paid to characterize the roughness by its frequency spectrum since for gate applications low frequency roughness components remain the key issue. We will show that optimized plasma treatment for LWR reduction may use plasma conditions leading to intense optical emission in the vacuum ultra violet (VUV) range (<200nm), and limiting the deposition of carbon outgassed resist byproducts on the pattern sidewalls. Moreover, we show that thermal process applied after plasma treatment can improve further the resist LWR, provided that no carbon deposition be previously formed on the resist sidewalls during the plasma treatment. The best available post-lithography treatment allows a 50% LWR reduction, while maintaining the critical dimension control. Finally, the developed AFM technique is used in comparison with CD-SEM to study the transfer of the reduced resist LWR resist into the gate stack during the patterning.