| AVS 60th International Symposium and Exhibition | |
| Plasma Science and Technology | Tuesday Sessions |
| Session PS2-TuM |
| Session: | Advanced FEOL/Gate Etching |
| Presenter: | M. Honda, Tokyo Electron Miyagi Limited, Japan |
| Authors: | M. Honda, Tokyo Electron Miyagi Limited, Japan K. Kobayashi, Tokyo Electron Miyagi Limited, Japan M. Yamato, Tokyo Electron Limited, Japan K. Oyama, Tokyo Electron Limited, Japan H. Yaegashi, Tokyo Electron Limited, Japan H. Mochiki, Tokyo Electron Limited, Japan |
| Correspondent: | Click to Email |
Due to the continued scaling in semiconductor industry, reducing line edge roughness (LER) and line width roughness (LWR) during photoresist mask pattern transfer by etch becomes increasingly important at 10nm and beyond.
Our previous studies showed that successful LER/LWR reduction was achieved by optimizing plasma treatment conditions and DC superposition (DCS) technology which is resist hardening by highly energetic electrons incident onto wafer in DC+RF hybrid capacitively-coupled reactor [1,2]. On the other hand, newly developed PMMA-based 193nm resist material with low etching durability has been proposed for the further reduction of LER/LWR [3,4].
In this paper, we investigated the effect and mechanism of DCS technology on newly developed 193nm resist material. As a result, we achieved LER=1.2nm with new 193nm resist material by etching durability enhancement of DCS technology. We also found that DCS technology is very effective for CD shrink control especially required for future BEOL patterning. This integrated solution of resist material modification and DCS technology will allow us for expanded process window for LER/LWR control at 10nm and beyond critical patterning etch.
Reference
[1] M. Honda et al., Proc. of SPIE 8328-09 (2012)
[2] M. Honda et al., AVS 59th Int. Symp. & Exhibit. (2012)
[3] H.Yaegashi et,al,. Proc. of SPIE 8325-11 (2012)
[4] K.Ohmori et, al., Proc. of SPIE 8325-12 (2012)