AVS 60th International Symposium and Exhibition
    Plasma Science and Technology Tuesday Sessions
       Session PS1-TuM

Paper PS1-TuM5
Si-Gate Etching in Radial Line Slot Antenna Plasmas: Control of Selectivity, Anisotropy and Loading

Tuesday, October 29, 2013, 9:20 am, Room 102 B

Session: Plasma Sources
Presenter: S. Voronin, TEL Technology Center, America, LLC
Authors: S. Voronin, TEL Technology Center, America, LLC
A. Ranjan, TEL Technology Center, America, LLC
H. Kintaka, TEL Technology Center, America, LLC
K. Kumar, TEL Technology Center, America, LLC
P. Biolsi, TEL Technology Center, America, LLC
Correspondent: Click to Email
Shrinkage of transistors as dictated by Moore’s law is required to make smaller, faster and less power-consuming devices at lower cost. 3-D gate transistors at 22nm technology node and beyond are needed to continue Moore’s law. To obtain all these advantages of 3-D transistors, their fabrication has stringent requirements to the etch process such as high anisotropy, high selectivity to Fin and Gate mask films and minimum loading between isolated and nested lines. In addition, precise control over the gate profile from a vertical to a slightly negative angle is important for integration purposes. In this work we present highly selective 3D gate etching in halogen-based Radial Line Slot Antenna plasma. Having spatially separated plasma generation and plasma processing regions, RLSATM etchers benefit of a very low electron temperature (Te~1eV) processing plasma discharge compared to conventional sources. Low electron temperature in the process plasma provides low dissociation rates of by-product and precursor gas, and ion bombardment of the structure at very low energies resulting in small iso-nested loading and very high process selectivity respectively. The ability of RLSATM plasma sources to operate in a very wide range of the pressures allows the etch process well above 100mT. This leads to further decrease of the electron temperature in the bulk and the ion energy, providing notch-free etching of the structure. Changing by-product re-deposition rate by O2 flow, etching times and bias power modulation regimes we can effectively control the gate profile from slightly tapered to slightly inversed tapered. Iso-nested delta can be minimized (and even reversed) by adjusting the process chemistry, bias power and pressure. Being very selective, RLSATM plasma process allows very long over-etching times without damaging the mask. This makes the process universal, minimizes wafer-to-wafer profile variation and effective for etching the structures where Si layer thickness varies across the wafer. It is shown that artificial increase of the plasma electron temperature in the chamber to ~2eV (an analog of a conventional plasma etcher) results in dramatic decrease of process selectivity to the oxide.