AVS 60th International Symposium and Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS-MoM

Paper PS-MoM1
Effects of Plasma-Induced Si Damage Structures on Annealing Process Design—Gas Chemistry Impact

Monday, October 28, 2013, 8:20 am, Room 104 C

Session: Innovative Chemistries for Advanced Etch Processes
Presenter: A. Matsuda, Kyoto University, Japan
Authors: A. Matsuda, Kyoto University, Japan
Y. Nakakubo, Kyoto University, Japan
M. Fukasawa, Sony Corporation, Japan
Y. Takao, Kyoto University, Japan
K. Eriguchi, Kyoto University, Japan
T. Tatsumi, Sony Corporation, Japan
K. Ono, Kyoto University, Japan
Correspondent: Click to Email

Plasma-induced Si substrate damage during shallow trench isolation, 3D-fin, and gate electrode formation processes have been believed to lead to “Si recess” (Si loss) [1] and latent defect generation resulting in performance degradation of metal–oxide–semiconductor field-effect transistor (MOSFET)—an off-state leakage (power consumption) increase [2] and the drain current (chip clock-frequency) decrease [3], respectively. Various plasma gas chemistries are employed for these Si etching processes. Regarding annealing process parameters, it was reported [4] that conventional thermal budgets could no longer be applied—the annealing temperature might be primal—in particular, in the case of hydrogen-containing plasmas (HBr/O2-and H2-processes). Based on this finding, two questions may be pointed out; (1) does this temperature-dependent feature hold for other plasmas? and (2) what is the principal mechanism? To answer these questions, Si-damage formation and the following annealing mechanisms were comprehensively investigated for various plasma processes (HBr/O2, H2, Ar, and He) and annealint conditions (750–1050C) in this study. An electrical capacitance–voltage (C–V) technique was employed to quantitatively evaluate the plasma-induced defect density, and a molecular dynamics simulations was carried out to study in detail the localized defect structures.

Silicon wafers covered with thermal oxide layer (2 nm) were damaged by various plasma processes and annealed in N2 ambient with various conditions. Defect densities before and after annealing were quantified by 1/C2-based analysis. It was found that the temperature-dependent damage-recovery dynamics holds for overall plasma processes, although H2- and He-plasma damage exhibit complicated features. We speculate that both the localized defect structure with its low density (1018-1019 cm-3) and the profile in the damaged region play major role in this mechanism—being confirmed also from molecular dynamics simulations. The present findings imply that not only the defect structure but also the profile in the damaged region should be identified in advance for designing the annealing conditions in future advanced MOSFET process technologies.

[1] M. Fukasawa et al.: J. Vac. Sci. Technol. A 29, 041301 (2011).

[2] K. Eriguchi et al.: J. Vac. Sci. Technol. A 29, 041303 (2011).

[3] K. Eriguchi et al.: IEEE Electron Device Lett. EDL-30, 1275 (2009).

[4] Y. Nakakubo et al.: AVS 59th Annual International Symposium and Exhibition, PS-MoM10 (2012).