AVS 60th International Symposium and Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS-MoA

Paper PS-MoA6
Fine Patterning of Copper by Plasma Etch Process for Advanced BEOL Interconnects

Monday, October 28, 2013, 3:40 pm, Room 104 C

Session: Advanced BEOL/Interconnect Etching
Presenter: H. Miyazoe, IBM T.J. Watson Research Center
Authors: H. Miyazoe, IBM T.J. Watson Research Center
M. Hoinkis, Applied Materials Inc.
B.N. To, IBM T.J. Watson Research Center
G. Fritz, IBM T.J. Watson Research Center
A. Pyzyna, IBM T.J. Watson Research Center
M. Brink, IBM T.J. Watson Research Center
C. Cabral, IBM T.J. Watson Research Center
C. Yan, Applied Materials Inc.
I. Ne’eman, Applied Materials Inc.
E.A. Joseph, IBM T.J. Watson Research Center
Correspondent: Click to Email

As device scaling continues beyond the 10 nm node, challenges in back end of line (BEOL) interconnect technology continue to multiply. Expanding beyond the known issues of patterning and integration of porous ultra low-k (ULK) materials, new issues such as line edge roughness and line width roughness (LER/LWR) as well as increased resistivity (emanating from grain boundary scattering) are only compounding the difficulties at hand and may require significant modifications to the typical damascene integration flow. Subtractive etching of Cu has a potential to overcome current difficulties in interconnects integration such as the increase of resistivity caused by electron scattering at grain boundary, poor coverage of liner/seed materials, and a time dependent dielectric breakthrough (TDDB) issue of ULK material by starting from blanket Cu film with large crystal (>1 μ m), by depositing it directly on Cu patterns, and by minimizing plasma damage during ULK etch, respectively. In this work, we examine one such alternative approach to conventional dual damascene copper integration, in which subtractive patterning of copper is employed. Successful patterning of copper at smaller than 50 nm critical dimension (CD) with smaller than 100nm in pitch is demonstrated using a novel high density plasma based dry etch process. Consisting of a reactive sputter based etch chemistry, appreciable etch rates on the order of ~15A/s are achieved, with high selectivity (>6:1) to masking layers. The angle of sidewall of approximately 85° was achieved at an optimized condition while we obtained ~45° in case of physical sputtering using pure Ar plasma. We confirmed that the resistivity of fabricate Cu line increases with the decrease of line CD. The resistivity of isolated Cu line at CD of ~30 nm is ranging from 10 to 20 μohm cm. A full review of the etch process, its mechanism and the positive implications on ULK materials, LER and LWR, metal resistivity and overall reliability will be discussed in detail.