| AVS 60th International Symposium and Exhibition | |
| Plasma Science and Technology | Monday Sessions |
| Session PS-MoA |
| Session: | Advanced BEOL/Interconnect Etching |
| Presenter: | P. Friddle, Lam Research Corp |
| Authors: | Y. Mignot, STMicroelectronics M. Beard, IBM B.G. Morris, IBM B. Peethala, IBM Y. Loquet, STMicroelectronics J.H. Chen, IBM S. Nam, GLOBALFOUNDRIES U.S. Inc. B. Nagabhirava, Lam Research Corp P. Friddle, Lam Research Corp |
| Correspondent: | Click to Email |
As feature critical dimension (CD) shrinks towards and beyond the 48nm pitch, new patterning techniques within the context of a trench-first-metal-hard-mask (TFMHM) patterning scheme have been developed to generate trenches and vias below 48nm pitch. One of the main challenges at advanced nodes is to create structures (i.e., trenches & vias) that can be robustly metalized. This requires several elements of focus for the etches: first, there must be zero dielectric etch damage that results in undercut of any hard masks in the film stack; second, the aspect ratio of the final etch structure must be minimized; and third, the shape of the trench or via profile must be tailored to be metallization-friendly (i.e., slight angle better than vertical) and finally a good selectivity on lower metallization in case of wet HMO faceting. These requirements often conflict with each other, especially within a patterning scheme that requires self-aligned vias, where the desired high selectivity to the hard mask conflicts with the need to minimize the amount of hard mask left in order to decrease aspect ratio. In this paper, we will discuss some of the approaches that we have investigated to achieve the best profile for metallization. This includes plasma etch all-in-one (AIO) dielectric etch optimization as well as multi-step solutions that potentially can use techniques including wet chemistries plus dry faceting and dry metal HMO removal. In addition, data will present on overview of the multi-patterning techniques such as multiple Litho-Etch (LE3), Sidewall Image transfer (SIT) and double patterning for self aligned via (DPSAV) to expose and understand the multiple underlying interactions at Dielectric RIE such as the SIT Block Mask with the DPSAV features.
This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities