AVS 60th International Symposium and Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS-MoA

Invited Paper PS-MoA1
Etching Challenges in the BEOL for sub 20nm Technology Nodes

Monday, October 28, 2013, 2:00 pm, Room 104 C

Session: Advanced BEOL/Interconnect Etching
Presenter: K. Kumar, TEL Technology Center, America, LLC
Authors: K. Kumar, TEL Technology Center, America, LLC
Y.P. Feurprier, TEL Technology Center, America, LLC
L. Wang, TEL Technology Center, America, LLC
J. Stillahn, TEL Technology Center, America, LLC
Y. Chiba, TEL Technology Center, America, LLC
A. Ranjan, TEL Technology Center, America, LLC
A. Metz, TEL Technology Center, America, LLC
A. Ko, TEL Technology Center, America, LLC
D.M. Morvay, TEL Technology Center, America, LLC
A. Selino, TEL Technology Center, America, LLC
P. Biolsi, TEL Technology Center, America, LLC
Correspondent: Click to Email
In the sub-32nm technology node, Trench First Metal Hard Mask (TFMHM) integration scheme has gained traction and become the preferred integration of low-k materials for BEOL. This integration scheme also enables Self-Aligned Via (SAV) patterning which prevents via CD growth and confines via by line trenches to better control via to line spacing. In addition to this, lack of scaling of 193nm Lithography and non-availability of EUV based lithography beyond concept, has placed focus on novel multiple patterning schemes. This added complexity has resulted in multiple etch schemes to enable technology scaling below 80nm Pitches, as shown by the memory manufacturers. Double-Patterning and Quad-Patterning have become increasingly used techniques to achieve 64nm, 56nm and 45nm Pitch technologies in Back-end-of-the-line. Challenges associated in the plasma etching of these integration schemes, along with the challenges posed with etching EUV resists, in concert with shape formation of the dual-damascene will be discussed in the presentation.