AVS 60th International Symposium and Exhibition
    Electronic Materials and Processing Wednesday Sessions
       Session EM-WeA

Invited Paper EM-WeA10
The Physics and Challenges of Realizing High Performance Group IV Tunnel Transistors

Wednesday, October 30, 2013, 5:00 pm, Room 101 B

Session: III-V Devices and Tunnel FETs
Presenter: J.C.S. Woo, University of California at Los Angeles
Authors: J.C.S. Woo, University of California at Los Angeles
H.-Y. Chang, University of California at Los Angeles
B. Adams, University of California at Los Angeles
P.-Y. Chien, University of California at Los Angeles
J. Li, University of California at Los Angeles
Correspondent: Click to Email

Reducing the standby power (IOFF* VDD) and operation power (CgVDD2*f) are crucial for low power application in MOSFET scaling. Hence, it becomes essential to lower IOFF and to scale VDD, and therefore devices with steep subthreshold swing (SS) are highly desired in low power application [1].

In conventional MOSFETs, the subthreshold swing is limited by thermal diffusion current (≥ 60mV/dec at T=300K). To overcome this limit, novel devices based on the band-to-band tunneling mechanism, namely tunnel FET (TFET), is proposed. It has been reported that TFETs can achieve ultra-high ION/IOFF under reduced VDD and steep SS (<60mV/dec), which makes it a competitive candidate for low power application [2-3]. However, reported results so far show that TFET can only provide small ION and achieve steep SS under low current level. These short comes may prevent TFET from entering main stream.

To resolve these challenges, it is important to understand the physics of TFET. Based on these insights, small band-gap materials such as SiGe and Ge have been proposed to improve carrier tunneling by lowering the tunnel barriers [4-5]. It is also critical to improve carrier tunneling (that is, reducing the tunneling distance) by enhancing lateral electric field across the tunneling junction. TFETs with dopant pocket between source and channel are reported as one of the devices to achieve small tunneling distance [6]. In this talk, n-i-p Si TFET with p+ pocket source fabricated by laser annealing is proposed and investigated. By the application of source pocket in TFET, the tunneling distance is reduced due to enhanced electric field across the tunneling junction. The steep SS (46mV/dec), excellent ION/IOFF ratio (>107) and improved output characteristics are observed in the experiment data at T=300K. The device performance of this TFET under low temperature measurement is also used to confirm the band-to-band tunneling mechanism. Finally, compared to other TEFTs, the TFET with source pocket is one of the most promising structures to improve the device characteristics of TFETs.

[1] R. Jhaveri et al., Trans. Elec. Dev., vol. 58, no. 1, pp. 80-86, 2011.

[2] F. Mayer et al., IEDM Tech. Dig., 2008, pp. 163–166.

[3] K. Jeon et al., VLSI Symp. Tech. Dig., 2010, pp. 121–122.

[4] D. Kazazis et al., Appl. Phys. Lett., vol. 94, no. 26, pp. 263508-1 – 263508-3, 2009.