Invited Paper EM-ThA3
Cu Interconnects at 1x Node - Challenges & Approaches

Thursday, October 31, 2013, 2:40 pm, Room 102 A

While much attention is focused on transistor innovation, it is interconnect performance that is

also now challenging Moore’s law because of its performance and scaling limitations. The last

time interconnects were overhauled for performance reasons was more than 15 years ago when

aluminum was replaced with copper interconnects fabricated in the revolutionary dualdamascene

architecture.

Copper dual-damascene interconnects provided superior lower resistance, and the incorporation

of porous low-k dielectrics into this architecture drove down the capacitance – together these two

materials have reduced RC delay and reduced energy consumption. However, the reduction of

the low-k dielectric constant has slowed in recent years. As they become more porous, these

dielectric materials become fragile, unable to cope with the mechanical stress that chips undergo

during packaging. They are not robust enough to maintain their low-k properties through the

dual-damascene process integration steps. In addition, the resistance of the interconnect is rising

dramatically because of three main factors: (i) the conventional tantalum nitride/tantalum highresistance

metallic barriers that block copper diffusion and prevent oxidation are taking up a

larger fraction of the metal interconnect cross-section, (ii) surface scattering increases as the

critical dimensions of the wires become smaller than the bulk mean free path of the electrons,

and (iii) grain boundary scattering increases as the copper grain size scales approximately with

the critical dimensions of the wires in dual-damascene fabricated interconnects. Hence, the RC

delay for interconnects has started to rise dramatically as the node shrinks beyond 22nm, driven

by the rise in resistivity for conventional damascene copper interconnects. This presentation

looks at process and integration-level inflections that promise to limit RC delay increase while

also achieving void-free gap fill in nano-scale interconnects.