AVS 60th International Symposium and Exhibition
    Electronic Materials and Processing Monday Sessions
       Session EM-MoA

Paper EM-MoA4
Sub 1-nm Ge-MOSFET with TiO2/Al2O3 Gate Stacks and Interface Trap Passivation by Forming Gas Anneal

Monday, October 28, 2013, 3:00 pm, Room 101 B

Session: High-k Gate Oxides for High Mobility Semiconductors II
Presenter: L. Zhang, Stanford University
Authors: L. Zhang, Stanford University
P.C. McIntyre, Stanford University
Correspondent: Click to Email

Equivalent oxide thickness (EOT) scaling is one of the most critical challenges for future Ge-MOSFET technology. It is difficult to achieve sub-1 nm EOT with a single dielectric material, due to the intrinsic trade-off between dielectric constants and band gaps. Recently, bilayer high-k materials, such as TiO2/Al2O3, HfO2/Al2O3, have been paid increasing attention. However, there are several challenges remaining for bilayer high-k stacks on Ge substrate: 1) an ultra-thin high-quality GeO2/GeOx layer is generally reported to be necessary for effective Ge surface passivation, but this is difficult to obtain by routine thermal oxidation. It has been reported that processes such as post-dielectric deposition plasma oxidation are beneficial for preparing such interface layers. 2) The interface between the two high-k materials in the bilayer must be abrupt and their thicknesses well-controlled, to reduce gate leakage as the EOT is scaled. In this paper, we address these challenges by a simple, low-temperature process flow using thermal annealing. Using carefully-controlled atomic layer deposition (ALD) of the dielectric layers and a forming gas anneal (FGA), a TiO2/Al2O3/Ge gate stack is demonstrated with EOT = 0.63 nm that achieves low Dit and gate leakage current density in MOS capacitors. Pt gated Ge-pMOSFETs with TiO2/Al2O3 gate stacks are fabricated, and have a sub-1nm EOT, 75 mV/dec subthreshold swing, 10m A/m m on state current and avoid gate metal/TiO2 reaction or interdiffusion.

In our process, a high quality Al2O3 layer on the Ge substrate is grown by atomic layer deposition with the help of efficient sites for Al(CH3)3 precursor adsorption produced by oxidant pre-dosing the Ge(100) surface prior to ALD. Forming gas anneal (FGA) is found to be a critical step to realize low interface trap densities in low EOT Ge transistors. We observed great improvement of device performance after FGA on both MOSCAPs and MOSFETs, the effectiveness of FGA determined by Al2O3 thickness, FGA conditions, and the identity of the overlying gate metal.

We have used both hard and soft x-ray synchrotron photoemission electron spectroscopy (PES) to investigate the Al2O3/Ge interface and the TiO2 layer in various Al2O3/Ge and Pt/TiO2/Al2O3/Ge structures before and after FGA. An increase in intensity of the Ge+4 feature is observed after FGA of Al2O3/Ge samples, and emergence of a detectable Ti +3 peak, consistent with loss of oxygen during FGA, is also identified in Pt/TiO2/Al2O3/Ge samples. Effects of these local chemical changes on the MOS performance of the resulting gate stacks will be discussed.