Paper TF-ThP17
Physical and Electrical Characteristic of Atomic Layer Deposition of Al_xHf_yO_z on Silicon

Thursday, November 1, 2012, 6:00 pm, Room Central Hall

In order to meet the increasing demand for high frequency electronic devices, the physical dimensions of MOSFETs have been continuously scaled down into nanoscale. However, one of the bottlenecks we encounter during the scaling-down process is the tunneling current leakage at the gates. SiO₂, the most commonly used traditional gate dielectric experiences an appreciable amount of tunneling current when the gate thickness is below 1-1.2 nm. And leakage greatly degrades the performance of nanoelectronics. Therefore, we propose using high-k dielectrics to replace SiO₂, which can effectively limit the tunneling leakage without losing the current control at gates. Our research has mainly focus on Al_xHf_yO_z deposited on silicon via Atomic Layer Deposition (ALD).The Aluminum to Hafnium ratio in the oxide is tuned to maximize the electrical and physical properties of the film. The electrical properties of each oxide will be characterized by fabricating transistors with gate oxide thicknesses of 5, 10, and 15 nm. Other than taking C-V and I-V measurements for capacitors and transistors, the films will be characterized by XPS, AFM, and spectroscopic ellipsometry. Finally, the effects of various annealing and deposition temperatures at the silicon-oxide interface will be studied using TEM.