AVS 59th Annual International Symposium and Exhibition
    Advanced Surface Engineering Tuesday Sessions
       Session SE-TuP

Paper SE-TuP1
Analysis of the Physical Damage during HBr/O2/Ar Gate Etching using Various Pulsed Plasmas

Tuesday, October 30, 2012, 6:00 pm, Room Central Hall

Session: Advanced Surface Engineering Poster Session
Presenter: K.Y. Jeon, Samsung Electronics Co. Ltd., Republic of Korea
Authors: K.Y. Jeon, Samsung Electronics Co. Ltd., Republic of Korea
J.Y. Lee, Samsung Electronics Co. Ltd., Republic of Korea
G.J. Min, Samsung Electronics Co. Ltd., Republic of Korea
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Recent device has been rapidly scaled. The plasma oxidation and lattice damage by energetic ions cause the silicon oxidation in the channel and source/drain regions of the transistors. In addition, they generate the defects such as the Si/SiO2 interface trap sites, contaminations, Si bond breaking and interstitial atoms. Those damaged regions by energetic ions can no longer be neglected. The continuous wave plasma is widely used in the conventional etch process, but it has some limitations to control the ion energy. It is difficult to reduce the damage layer in the atomic scaled device.This various plasma conditions in Gate etch process affect the physical damage on the substrate Si lattice and the gate oxide. In this work, the Si damage has been compared after etching by various plasma generation methods. Si etches has been performed in ICP chamber by using continuous wave HBr/O2/Ar plasmas, bias pulsed HBr/O2/Ar plasmas, synchronous pulsed HBr/O2/Ar plasmas, and especially DC pulsed plasma. Ellipsometry and TEM were used to analyze the Si lattice damage. Plus some electrical tests such as time zero dielectric breakdown (TZDB), charge pumping current, C-V measurement respectively. As a result, the pulsed plasma etching method is promising alternatives in respect of the physical Si damage, including the charge build-up and etch uniformity, and the mask selectivity