AVS 59th Annual International Symposium and Exhibition
    Electronic Materials and Processing Tuesday Sessions
       Session EM-TuM

Invited Paper EM-TuM11
Trapping Centers in High -k Dielectrics for MOS Devices

Tuesday, October 30, 2012, 11:20 am, Room 009

Session: Electrical Testing and Defects in III-V’s
Presenter: P. Lenahan, Pennsylvania State University
Correspondent: Click to Email
This presentation will review experimental evidence with regard to trapping centers in high dielectric constant gate stacks in metal oxide semiconductor (MOS) devices. The presentation will deal primarily with hafnium oxide based systems on silicon. The presentation will include discussion of silicon/dielectric interface traps, trapping centers within the interlayer dielectric between the silicon and the high -k material, and defects in hafnium oxide. Most of the experimental evidence with regard to the physical and chemical nature of these trapping centers comes from electron paramagnetic resonance (EPR) and electrically detected magnetic resonance (EDMR). The presentation will thus emphasize EPR and EDMR measurements along with "electronic" measurements on these systems. An attempt will be made to link device processing, defect structures, and defect densities to the electronic proprieties of these high -k MOS systems.