Invited Paper EM-TuM1
Characterization, Modeling and Control of Fermi Level Pinning Phenomena at III-V High-k MOS Gate Stack Interfaces

Tuesday, October 30, 2012, 8:00 am, Room 009

III-V high mobility channel materials are currently drawing attention as possible material candidates for devices to continue scaling of CMOS transistors on the Si platform. Here, construction of high performance high-k MOS gate stacks is the key issue. Such gate stacks are also needed for various gate controlled III-V nanowire and nanodot devices for “Beyond CMOS” applications.

The purpose of this paper is to review the present status of understanding and control of “Fermi level pinning (FLP)” phenomena at III-V metal-gate high-k gate stack interfaces whose atomic level control is vitally important for success of above approaches. FLP at the insulator-semiconductor (I-S) interface deteriorates efficiency and stability of gate control of carriers while FLP at the metal-insulator (M-S) interface deteriorates the control capability of the threshold voltage of the MOSFET.

First, various models on FLP at I-S and M-S interfaces are reviewed, paying attention to chemical trends of pinning at Schottky barriers and MOS capacitors formed on GaAs and other III-V materials. Extremely complicated C-V behavior of ALD high-k dielectric/GaAs MOS capacitors is explained by the authors' disorder induced gap state (DIGS) model [1] where a U-shaped donar-acceptor gap state continuum causes pinning. Importance of the location of the charge neutrality level (CNL) [2] is pointed out for channel material selection, showing superiority of InGaAs over GaAs and others.

Then, various efforts to remove FLP at III-V I-S interfaces by inserting interface passivation layers are reviewed. In particular, authors' efforts to realize pinning-free high-k MOS interfaces on GaAs and InGaAs, using the silicon interface control layer (Si ICL) are described. Here, the Si ICL is an MBE-grown ultrathin Si interlayer which is proposed first by the authors [2,3] and now extended　to construction of high-k MOS gate stacks. The structure has been investigated by XPS, contactless C-V and STM/STS methods and by ex-situ PL and MOS C-V measurements [4-7].

Finally, the FLP issue at metal-high-k Schottky interfaces is briefly discussed.

[1]H. Hasegawa and H. Ohno, J. Vac. Sci.Technol, B4, 1130 (1986) [2]H. Hasegawa, M. Akazawa et al J. Vac. Sci. Technol. B 7, 870 (1989).[3]H. Hasegawa, M. Akazawa, et alJpn. J. Appl. Phys.. 27, L2265 (1988) [4]M. Akazawa and H. Hasegawa, J. Vac. Sci. Technol. B25, 1481(2007)[5]M. Akazawa and H. Hasegawa, J. Vac. Sci. Technol. B26,(2008)1569 [6]M. Akazawa, A.Domanowska, B. Adamowicz and H. Hasegawa, J. Vac. Sci. Technol. B27, 2028(2009) [7]M. Akazawa and H. Hasegawa, Appl. Surf. Sci., 256, 5708(2010)