The rapid introduction of different interconnect schemes enabled sustained scaling towards advanced technology nodes. Enablers are dimensional and material scaling together with system level aspects. Both logic and memory chips require tight pitch interconnecting lines with some common aspects and at the same time some different requirements. From material and dimensional scaling point of view logic interconnects demand tight pitch metal lines with low-k dielectrics, while emerging memories demand high current (or voltage) through tight pitch metal lines embedded into silicon oxide or air gaps. Conventional interconnects are built using multilevel damascene recently added with multiple patterning techniques leading to increased complexity. In order to break down the barrier and pave the way for 10nm technologies and beyond further material innovation along with non-conventional integration schemes and potentially system architecture modification will be necessary. Copper interconnects will require less than 2nm cladding layer or eventually the complete omission of conventional Ta-based diffusion barriers. Copper based metallization is expected to extend to 15nm critical dimensions although the number of elements through alloying and various liners increases already today. At 10nm and below alternatives to Cu wiring without a reliability issue is a candidate. For thin film deposition self assembled mono-layers, electroless and CVD/ALD techniques are becoming important, while novel dielectrics increasingly rely on self-assembling chemistries. This talk will focus on options that are being considered for 10nm and beyond. While several aspects will be mentioned, the main emphasis will be put on material innovation. Examples and case studies will be detailed for dielectric and metal options along with the relevant material characterization. Examples include defect characterization in low-k materials, phase identification and stress measurements in metal lines.