AVS 59th Annual International Symposium and Exhibition
    Electronic Materials and Processing Tuesday Sessions
       Session EM-TuA

Paper EM-TuA12
Metallization Challenges in Integration of Soft Dielectric Materials

Tuesday, October 30, 2012, 5:40 pm, Room 009

Session: Materials and Processes for Advanced Interconnects
Presenter: R. Chebiam, Intel Corporation
Authors: R. Chebiam, Intel Corporation
C. Jezewski, Intel Corporation
B. Krist, Intel Corporation
H. Yoo, Intel Corporation
J. Clarke, Intel Corporation
Correspondent: Click to Email
In order to take advantage of reduction in transistor gate delay at smaller dimensions, back-end interconnect (RC) delay has to be minimized. One of the methods of reducing the system capacitance is by reducing the dielectric constant of ILD's at each technology node. There is an observed trend that modulus and hardness of dielectric films degrades with decreasing k value. This is either due to increased carbon content or increased porosity. Ultra low-k materials (k<2.2) are well known to be susceptible to damage during the patterning process. However, there has been little focus on the damage resulting from the metallization process (barrier/seed, plate, and CMP).In this study we use a spin-on dielectric (K~2.2) with E =4.5GPa and H= 0.3GPa to investigate metallization damage. The soft ILD shows little feature size blowout post metallization for large feature sizes (>100nm). However, features size blowout of ~10-18 % is seen for sub 100nm features post metallization compared to pre-metallization. Feature blow out appears to be driven by dielectric densification and to a less extent from material etch out. Densification damages the dielectric by increasing the k value and hence must be minimized. The origin of the feature size blowout can be traced to an energetic barrier or seed deposition process. For example, a high resputter PVD barrier process has similar blowout compared to an ALD Liner process. When the energy of barrier /seed process was decreased blowout was reduced, but this was accompanied by poorer sidewall coverage which will result in degraded gapfill and reliability. The key challenge can then be highlighted as developing a low energy barrier/seed process that has good sidewall coverage (conformality) and no feature blowout to enable ultra low-k dielectrics integration.