AVS 59th Annual International Symposium and Exhibition
    Electronic Materials and Processing Thursday Sessions
       Session EM-ThP

Paper EM-ThP7
Protoype of Junctionless Transistor on SOI Wafers using Focused Ion Beam Milling

Thursday, November 1, 2012, 6:00 pm, Room Central Hall

Session: Electronic Materials and Processing Poster Session
Presenter: L. Petersen Barbosa Lima, State University of Campinas, Brazil
Authors: L. Petersen Barbosa Lima, State University of Campinas, Brazil
J. Alexandre Diniz, State University of Campinas, Brazil
I. Doi, State University of Campinas, Brazil
J. Godoy Filho, State University of Campinas, Brazil
H. Ivanov Boudinov, University of Rio Grande Do Sul, Brazil
Correspondent: Click to Email
Nowadays, Junctionless devices (JL) have gained much attention of microelectronics industry, because it is compatible with CMOS technology and can be useful for 3D devices. In this context, nMOS JL devices were fabricated on SOI substrates using Ga+ Focused Ion Beam (FIB) milling and for depositions of SiO2 (gate dielectric) and Pt layers (as gate, drain and source electrodes) of JL transistor. In this work, two methods to fabricate the JL devices were used. One method is using on FIB system to milling the Si substrate and the other method used Reactive Ion Etching (RIE) and FIB system to etch the Si substrate. The samples with only FIB system were called JLFIB and samples with RIE plasma etch and FIB system were called JLRFIB. First of all, the wafers JLFIB and JLRFIB were doped with phosphorus, dose 1019 cm-3 and energy of 30 KeV, using ion implantation system. After that, Rapid Thermal Annealing (RTA) were used to anneal the SOI samples after the ion implantation procedure. 0.6-µm-thick SiO2 were obtained using a wet oxidation on conventional furnace to get thinner height of Si substrate on SOI waffer. So, litography to define MESA structures and RIE SI etching were carried out only on JLRFIB samples. Then JLFIB and JLRFIB samples were insert on FIB system to get the JL fabrication. First of all, using a Ga+ ion beam the Si substrates were milled to obtain the Si nanowire to define the gate, drain and source regions of JL transistor. Width, length and height dimensions of Si nanowire were about 100 nm, 4 µm and 50-80 nm, respectively. Then, 10-nm-thick SiO2 was deposited to be gate dielectric and finally, Pt were deposited to be gate, drain and source electrodes. Energy Dispersive X-Ray Spectroscopy (EDS) measurements were carried out to confirm the surface composition of Si nanowire, SiO2 gate dielectric deposition and Pt electrodes deposition. In addition, EDS results show some Ga incorporation on Si nanowire surface, however, this incorporation was derived from Ga+ FIB and no significant damage on Si nanowire was occurred. Finally, these devices were sintered in a conventional furnace in forming gas at 450°C for 10 and 20 minutes. Drain-source current (Id) x drain-source voltage (Vds) measurements of JLFIB and JLRFIB devices were carried out, and indicate that the devices are working, like a gated resistor or JL device, with high Pt source and drain contact resistances, which lead to the distortions of Id x Vds curves. However, these distortions can be reduced using a longer time of contact sintering process and a Si nanowire height lower than 50 nm. Finally, our fabrication method using FIB process steps can be used to obtain JL devices.