Invited Paper EM+TF+OX+GR-MoA7
Ultimate Scaling of High-k Gate Dielectrics: Current Status and Challenges

Monday, October 29, 2012, 4:00 pm, Room 009

Current status and challenges of aggressive equivalent-oxide-thickness (EOT ) scaling of high-k gate dielectrics via higher-k (>20) materials and interfacial layer (IL) scavenging techniques are reviewed [1]. La-based higher-k materials [2, 3] and La-silicate IL with HfO₂ [4] showed aggressive EOT values (0.5–0.8 nm), but with large effective workfunction (EWF) shifts toward the Si conduction band edge, limiting their application to nFET. Further exploration for pFET-compatible higher-k materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-k dielectrics to future nodes [4, 5]. Remote-scavenging techniques enable EOT scaling below 0.5 nm. We will review IL scavenging techniques from the viewpoints of (1) IL growth condition; (2) Choice of scavenging element; (3) Location of scavenging element; (4) Choice of high-κ material and (5) Maximum process temperature. Careful choice of materials and processes based on these considerations is indispensable. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling is accompanied with loss of EWF control [6] and with severe penalty in reliability [7]. Therefore, highly precise IL thickness control in an ultra-thin IL regime (<0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

This work was performed by the Research alliance Teams at various IBM Research and Development Facilities.