Paper EM+TF+OX+GR-MoA4
Electrical and Physical Characteristics of High-k/Metal Gate MOS Devices on MBE-Grown Germanium on Silicon Using Aspect Ratio Trapping

Monday, October 29, 2012, 3:00 pm, Room 009

Due to its high hole mobility and relative compatibility with Si CMOS processing, Ge has long been considered as a replacement channel material for PMOS devices. Selective area growth of Ge channels on bulk Si substrates would be ideal for minimizing fabrication costs and allowing the co-implementation of other materials (III-Vs for NMOS). However, due to the 4.2% lattice mismatch between Ge and Si, unacceptably high dislocation densities (~10⁹ cm^-2) are created during this heteroepitaxy.

In this work, we investigate the fabrication of MOS gate stacks on MBE-grown Ge on Si using Aspect Ratio Trapping (ART)^1,2 to reduce Ge defect density. ART is a growth technique that allows for the reduction of defects for lattice mismatched materials by trapping the threading dislocations into the sidewalls of patterned nanoscale trenches in which the epitaxial growth takes place. This technique has the added benefit of producing the necessary geometric structure required for highly scaled tri-gate devices while reducing defect density simultaneously. Surface roughness and defect density dependence on growth temperature and growth rate will be discussed as will be the effect of varying the trench geometry. RHEED, XRD, XPS, TEM, EPD, AFM, SEM, and IPE data are correlated with growth conditions to produce high quality heteroepitaxial growth. Data will be presented demonstrating the use of low-temperature buffer layers in conjunction with low-growth rate bulk Ge results in a reduction in threading dislocations of 2-3 orders of magnitude.

MOS devices were fabricated on the MBE-grown Ge on Si samples. A high-quality interface was obtained using a DI-H₂O surface functionalization by pre-pulsing the H₂O 50 times in the atomic layer deposition (ALD) chamber at 250 °C.³ A thin interfacial Al₂O₃ film was deposited by ALD at 250 °C followed by forming gas anneal (FGA) performed for 30 minutes at 350 °C. This FGA step converts the surface functionalized oxide to a thin layer of GeO₂ resulting in improved electrical performance. 2.5 nm of HfO₂ was then deposited by ALD. 10 nm of RF sputtered TiN was deposited as the gate metal followed by low-temperature anneals in various ambients to tune the effective work function of the HfO₂/TiN gate stack.⁴ A final FGA for 30 minutes at 350 °C completed device processing. These devices show excellent PMOS characteristics and will be discussed.

This work is supported by the SRC Global Research Corporation.

1 J.-S. Park, et al., Appl. Phys. Lett. 90, 052113 (2007).

2 J. Bai, et al., Appl. Phys. Lett. 90, 101902 (2007).

3 S. Swaminathan, et al., J. Appl. Phys. 110, 094105 (2011).